Novel design for testability schemes for CMOS ICs

Favalli, M.; Olivo, P.; Damiani, M.; Riccò, B.

doi:10.1109/4.62148

Cited by 43 publications

(27 citation statements)

References 5 publications

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“…Much recent research has been devoted to the development of effective BICS' and several schemes have been proposed (Nigh and Maly 1989;Favalli et al 1990;Maly and Patyra 1992;Miura and Kinoshita 1992;Shen, Daly, and Lo 1993;Rajsuman 1995;Tang et al 1995;Kim, Hong, and Kim 1998). Because of these efforts, the current sensing ability has been greatly enhanced.…”

Section: International Journal Of Electronicsmentioning

confidence: 98%

“…95, No. 10, October 2008, 999-1007 (Keating and Meyer 1987;Favalli, Olivo, Damiani, and Ricco 1990;Tang, Lee, and Liu 1995): a) it can reduce test equipment cost; b) the testing rate can be increased; c) it can improve the detectability and observability of faults in the CUT; d) higher current sensing resolution can be achieved and e) it can avoid the influence of I/O current, which may dominate the total chip's current.…”

Section: Introductionmentioning

confidence: 98%

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Current monitoring circuit for fault detection in CMOS integrated circuit

Kim

2008

International Journal of Electronics

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This article presents a built-in current sensor (BICS), which detects faults using the current testing technique in CMOS integrated circuits. This circuit employs crosscoupled PMOS transistors, which are used as current comparators. The proposed circuit has a negligible impact on the performance of the circuit under test (CUT). In addition, no extra power dissipation and high-speed fault detection are achieved. It can be applied to deep sub-micron processes. The validity and effectiveness are verified through the HSPICE simulation on circuits with faults. The entire area of the test chip is 116665 mm 2 . The BICS occupies only 41617 mm 2 of the area of the test chip. The area overhead of a BICS versus the entire chip is about 9.2%. The chip was fabricated with Hynix 0.35 mm 2-poly-4-metal N-well CMOS process.

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Section: International Journal Of Electronicsmentioning

confidence: 98%

Section: Introductionmentioning

confidence: 98%

Current monitoring circuit for fault detection in CMOS integrated circuit

Kim

2008

International Journal of Electronics

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“…As an alternative, the use of a sensing circuit [5] or of stability checking flip-flops [6] has been proposed. Both these circuits provide a delay error indication, but they cannot simultaneously bring information about the correctness of the monitored signal in the absence of delay errors.…”

Section: Introductionmentioning

confidence: 99%

Sensing circuit for on-line detection of delay faults

Favalli

Metra

1996

IEEE Trans. VLSI Syst.

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Abstruct-A sensing circuit for on-line testing of delay faults is presented. It can be used to monitor the outputs of circuits that are either general, or designed to be self-checking with respect to steady-state er". Detailed analyses of the proposed circuit have shown that it is preferable to alternate solutions from the point of view of both the accuracy and the self-testing capability that make it suitable for self-checking applications. Checking architectures for delay faults, making use of the proposed sensing circuit and of standard checkers, are presented.

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“…From a functional point of view, such a circuit is an 8-way multiplexer (Fig. l), whose basic macrogates (hereafter called Cells) include the DFT techniques described in The "Analog Fault Test Bloclt" and "Delay Fault Test Block" implement t.he t,echnique described ill [5] The power supply and ground of the functional circuit are separated also from those used for the 1 / 0 buffers, thus IDDQ can be nieasnred without the need to eliminate undesired contributions due to large blocks of unaffected circuitry.…”

Section: The Chip Used For Experimentsmentioning

confidence: 99%

An implementation of CMOS design for testability techniques for non stuck-at faults

Lanzoni

Favalli

Olivo

et al.

ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures

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The paper presents an experimental analysis of DFT techniques used to detect the presence of faulty resistive paths throughout CMOS ICs. Current monitoring, delay fault testing and new design for testability (DFT) techniques are compared by means of a chip designed ad hoc, that allows to simulate via hardware the presence of resistive bridgings within standard functional blocks. The results presented in this work suggest that specific DFT techniques offer considerable advantages over more conventional approaches.

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Novel design for testability schemes for CMOS ICs

Cited by 43 publications

References 5 publications

Current monitoring circuit for fault detection in CMOS integrated circuit

Current monitoring circuit for fault detection in CMOS integrated circuit

Sensing circuit for on-line detection of delay faults

An implementation of CMOS design for testability techniques for non stuck-at faults

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