Novel design of Address Generator for WiMAX multimode interleaver using FPGA based finite state machine

Upadhyaya, Bijoy Kumar; Iti, Saha Misra; Sanyal, Sugata

doi:10.1109/iccitechn.2010.5723846

Cited by 15 publications

(12 citation statements)

References 2 publications

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“…The work in [3] shows the grouping of incoming data streams in to block to reduce the frequency of memory access in a deinterleaver using conventional look up table based address generator in WiMAX system. The work in [5] shows that, it is finite state machine based technique is used to generate the address for interleaver/deinterleaver in WiMAX system.…”

Section: Related Workmentioning

confidence: 99%

Design of efficient viterbi technique for interleaving and deinterleaving

Surya¹,

Mohanraj²

2015

2015 2nd International Conference on Electronics and Communication Systems (ICECS)

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Communication System is a collection of individualcommunications network, transmission systems, relay stations, tributary stations and data terminal equipments. In transmission system wireless communication is the transfer of information between two or more points that are not connected by an electrical conductor. WiMAX is the wireless communication standard designed to provide 30 to 40 Mega bits per second data rates. WiMAX as a standards based technology enabling the delivery of last mile wireless broadband access as an alternative to cable and DSL. WiMAX can provide at home or mobile internet access across whole cities or countries. The address generation of WiMAX is carried out by interleaver and deinterleaver. Interleaving is used to overcome correlated channel noise such as burst error or fading. The interleaver/deinterleaver rearranges input data such that consecutive data are spaced apart. The interleaved memory is to improve the speed of access to memory. The viterbi technique reduces the bit error rate.

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Section: Related Workmentioning

confidence: 99%

Design of efficient viterbi technique for interleaving and deinterleaving

Surya¹,

Mohanraj²

2015

2015 2nd International Conference on Electronics and Communication Systems (ICECS)

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“…. , (Ncbps/d) -1represent the row and column numbers, respectively, inTable-1 [5]. In addition, kn represents the deinterleaver addresses.…”

Section: Table-1: Address Generation Of Different Schemesmentioning

confidence: 99%

“…A column counter CLC0 with multiplexer M0 and comparator C0 generate the variable column numbers to implement permissible Ncbps. A multiplier ML0 and an adder A0 perform the desired operations to implement (5). The address generator for 16-QAM follows a similar structure, such as that of QPSK with few additional modules.…”

Section: Table-1: Address Generation Of Different Schemesmentioning

confidence: 99%

“…The channel interleaver permutes the encoded bit stream to reduce the effect of burst error. When convolutional turbo code (CTC) is used for FEC, being optional in WiMAX, the channel interleaver is not required, since CTC itself includes an interleaver within it [5]. Modulation and construction of orthogonal frequency-division multiplexing symbols are performed by the two subsequent blocks, namely, mapper and inverse fast Fourier transform of Fig.…”

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confidence: 99%

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Design and Implementation of Address Generator for Wimax Deinterleaver on Fpga

Naykodi¹

2014

IJRET

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This Paper enumerates efficient method of address generator for WiMAX Deinterleaver using verilog coding. It is a low-complex, high speed and resource efficient method because it eliminates the requirement of floor function. The use of an internal multiplier of FPGA and the sharing of resources for quadrature phase-shift keying (QPSK),16-quadrature-amplitude modulation (QAM), and 64-QAM modulations along with all possible code rates makes our approach to be novel and highly efficient when compared with conventional look-up table-based approach. The proposed approach exhibits significant improvement in the use of FPGA resources.

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“…The WiMAX block interleaver/de-interleaver exploits different Interleaver depths (N cbps ) to incorporate various code rates and modulation schemes and isdescribed in standard documentfor IEEE 802.16e [6]. The Encoded data bits received from CC are interleaved by a block interleaver using two step processes [7]. The first step ensures that the adjacent coded bits are mapped onto nonadjacent subcarriers, which provides frequency diversity and improves the performance of the decoder.…”

Section: Interleaving / De-interleaving In Wimaxmentioning

confidence: 99%

Memory Efficient LUT Based Address Generator for OFDM-WiMAX De-Interleaver

Upadhyaya¹,

Goswami²,

Sanyal³

2014

IJEEE

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In this paper, a memory efficient Look-up Table (LUT) based address generator for the de-interleaver used in OFDM-WiMAXtransreceiver is proposed. The relationships between various address LUTs implementing different interleaver / de-interleaver depths within a modulation scheme have been exploited to model the proposed address generator. The proposed design shows 81.25% saving of memory blocks in comparison with conventional technique. Hardware structure of the address generator is developed and is converted into a VHDL model using Xilinx Integrated Software Environment (ISE). Simulation results obtained using ModelSim XE-III verifies the functionality of the proposed design. Comparative study of FPGA implementation results of the design on two different platforms is presented. Performance improvement of approximately 30% in terms of maximum operating frequency over a recent work is also obtained.

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Novel design of Address Generator for WiMAX multimode interleaver using FPGA based finite state machine

Cited by 15 publications

References 2 publications

Design of efficient viterbi technique for interleaving and deinterleaving

Design of efficient viterbi technique for interleaving and deinterleaving

Design and Implementation of Address Generator for Wimax Deinterleaver on Fpga

Memory Efficient LUT Based Address Generator for OFDM-WiMAX De-Interleaver

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