Novel dielectric slots in Cu interconnects for suppressing stress-induced void failure

Lim, Y.K.; Pey, K. L.; Tan, Juan Boon; Lee, T.J.; Vigar, David; Hsia, Liang Choo; Lim, Yoon-Soo; Kamat, N.R.

doi:10.1109/iedm.2005.1609300

Cited by 5 publications

(9 citation statements)

References 8 publications

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“…Small dielectric blocks that are commonly used in wide Cu metal leads to prevent dishing during chemical mechanical planarization process were redesigned in an attempt to suppress stressinduced void failure in Cu interconnects [18,19]. For stress migration (SM), the process of void nucleation is strongly driven by hydrostatic stress.…”

Section: Effect Of Dielectric Slot On Stress Migrationmentioning

confidence: 99%

Finite element analysis of thermal stress for different Cu interconnects structure

Wang

Feng-li

Gao

2012

Microelectronics Reliability

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Section: Effect Of Dielectric Slot On Stress Migrationmentioning

confidence: 99%

Finite element analysis of thermal stress for different Cu interconnects structure

Wang

Feng-li

Gao

2012

Microelectronics Reliability

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“…On the other hand, as shown in Fig. 4.5(b), no voiding was observed in the presence of a dielectric slot close to the via [95]. The impact of dielectric slot on the interconnects resistance was minimal, i.e.…”

Section: Effect Of Dielectric Slots On Stress Migration Reliabilitymentioning

confidence: 83%

“…The impact of dielectric slot on the interconnects resistance was minimal, i.e. ~1.7% increment [95]. Further studies were carried out by G.D.R.…”

Section: Effect Of Dielectric Slots On Stress Migration Reliabilitymentioning

confidence: 99%

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Effect of stress migration on electromigration for nano scale advanced interconnects

Heryanto¹

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“…The higher tensile stress and the higher effective diffusive volume of vacancies, lead to the formation of the stress-induced void beneath the inner via only. In addition, the study of the effect of metallization width on [35]. Several examples of the dielectric slot designs are proposed in Fig.…”

Section: Discussionmentioning

confidence: 99%

Stress migration study of Cu/Low-k interconnect system

Lim¹

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The demand for high performance, high packing density and low power dissipation integrated circuits (IC) has caused downward scaling of feature sizes in very large-scale integration (VLSI) fabrication. However with the scaling of interconnect feature size; the interconnect delay, which is one of the key factors determining the overall performance of devices is severely penalized [1]. Therefore copper (Cu), which is well known for its lower resistivity and excellent resistance to electromigration (EM) and stress-induced voiding as compared to aluminum (Al) and its alloy, was introduced as the material for nanoscale interconnects [2-9]. However, when the efforts to develop an effective Cu etch process failed, dual damascene which is an elegant technique of inlaying metal for interconnects throughout the back-end-of-line (BEOL) becomes the preferred choice. Even though Cu dual damascene has already been proven to be process-friendly and costs effective, its reliability robustness is strongly process and structural dependent. Starting from 0.13 µm process, yield and reliability have become critical issues for the integration of Cu and low-k dielectrics. Poor yield is observed at wafer sort and even for those apparent good chips; the failure rates are unacceptable during accelerated life testing. Physical analysis has shown the formation of stress-induced voids to be either within or beneath vias [10-35]. As such, understanding on the phenomena of stress-induced voiding in Cu interconnects must be established so as to resolve these issues.

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Novel dielectric slots in Cu interconnects for suppressing stress-induced void failure

Cited by 5 publications

References 8 publications

Finite element analysis of thermal stress for different Cu interconnects structure

Finite element analysis of thermal stress for different Cu interconnects structure

Effect of stress migration on electromigration for nano scale advanced interconnects

Stress migration study of Cu/Low-k interconnect system

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