Interconnects in very large scale integration (VLSI) chips are susceptible to failure due to stress migration (SM) and electromigration (EM). At use condition, these two failure mechanisms play a collective role in causing interconnect failure. We present a study on SM and EM interaction in lower (MX structure) and upper metal (MX+1 structure) of dual-damascene Cu/low-κ interconnects. It is found that both mechanisms are dependent; statistical analysis shows that EM failure time is affected by the presence of residual stress induced by SM. This effect was more severe in the lower metal, where the EM median-time-to-failure (t50) for the majority of samples could be degraded by 30%–60%. For the upper metal of Cu interconnects, the t50 is degraded by about 10%. The reliability implication of the residual stress in copper interconnects on the EM is further investigated with various failure analysis techniques and three-dimensional finite element simulation. It is proposed that SM can influence EM when there is significant amount of vacancy accumulation due to SM in the cathode area which accelerates EM nucleation time. In the case of the MX structure, our experimental results show that SM and EM interaction occurs exactly below the via at the MX cathode side, leading to abrupt failures. On the other hand, in MX+1 structure, vacancies are likely to accumulate at the edge of upper metal lead during SM test, thus accelerating the failure during subsequent EM test. A failure mechanism model for stress evolution and void formation is proposed to provide insight into the interaction between these two failure mechanisms.

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