Novel DRAM mitigation technique

Bougerol, A.; Miller, F.; Buard, N.

doi:10.1109/iolts.2009.5195991

Cited by 3 publications

(3 citation statements)

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“…Unfortunately, this structure requires too many modifications in several components to hinder the quick adoption of PCM. In [3], although triple redundancy technique could cover any number of upset in a given word, it incurs larger overheads in terms of area and power consumption. Differently from the previous approaches, Li et al adopt error correction codes (ECC) to increase the reliability effectively [4][5] [6].…”

Section: Introductionmentioning

confidence: 99%

A fault-tolerant SDRAM controller based on a dynamically reconfigurable shift register chain

Lou

Cui

Pei

et al. 2014

2014 IEEE International Conference on Progress in Informatics and Computing

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A SDRAM like conventional memories can be affected by the occurrence of single event upsets (SEUs) which can lead to serious faults such as single-bit error. In order to cope with this effect of SEUs, a fault-tolerant SDRAM controller is proposed instead of previous approaches that required modifications to the internal structure of the SDRAM itself. For one thing, an optimized encoder and decoder based the (40, 32) Hamming code are integrated to eliminate the problem of single-bit error. Moreover, in the context of error correction, a write request shift register chain is adopted to prefetch the subsequence write requests, and simultaneously a data correction shift register chain is applied to hide the delay of write-back into the following accesses. Besides, with the dynamic combination of two chains, a reconfigurable new chain can be generated to achieve the goal that the burst read data, corrected data and requested write data can be issued seamlessly. Simulation results show that, the optimized encoder and decoder reduce 16.45% area overhead with the slight delay, and the proposed structure could also reduce 11.2% execution time of the test program.

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Section: Introductionmentioning

confidence: 99%

A fault-tolerant SDRAM controller based on a dynamically reconfigurable shift register chain

Lou

Cui

Pei

et al. 2014

2014 IEEE International Conference on Progress in Informatics and Computing

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“…But because the density of SRAMs is lower than DRAMs, fewer cells will be upset per unit strike. Figure 2.7 displays the "insensitive state" of a DRAM cell [51] (i.e. the state of the storage capacitor which cannot be modified by radiation).…”

Section: Memory Systemsmentioning

confidence: 99%

“…Because only one state of a DRAM cell is sensitive to radiations (unidirectional errors) the authors in [51] propose a new mitigation technique used for detecting errors. The idea is based on finding the insensitive state of a DRAM cell and then storing the opposite value (which corresponds to the charged state) as the reference value in a cell.…”

Section: Self-healing Memory Systems Through Error Detection and Corr...mentioning

confidence: 99%

Self-healing and secure low-power memory systems

Neagu

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The main objective of this thesis is to bring new contributions to the self-healing and secure systems domain. In particular, to develop a self-healing technique for memory systems and to increase security of memory systems, techniques which favor low-power consumption. In order to achieve the main objective, three major research objectives were proposed: design of an error detection and correction scheme for errors that occur in memory systems and integrate them in a memory system, design techniques to increase the security and data privacy of memory systems against different types of attacks and to combine the previous two into a single solution, in order to achieve a self-healing and secure low-power memory system. The low-power aspect of the proposed solutions and techniques is evaluated during design stage and afterwards through simulation. Also, the architectures are evaluated from several other points of view, such as error detecting and correcting performance, area and delay overhead, and security efficiency. The first chapter contains a short introduction of the domain and subject of the thesis, current state of the art in this domain, proposed objectives and thesis organization. The second chapter contains a unidirectional error detecting, correcting and localization scheme, which is used for the self-healing technique. The chapter begins with an introduction and motivation about error detecting and correcting codes and their usage in memory systems and continues with a theoretical background. The chapter continues with the design of the proposed codes, which are explained in detail and illustrated through several figures. Then, they are analyzed from the following points of view: coding scheme, error localization, error correction and error escapes. For the latter three, metrics are defined, in order to evaluate the codes. Afterwards, the implementation of the proposed codes is exposed in several figures. Also, the usage of the codes is explained, as well as DRAM repair strategies. In the end of this chapter, the efficiency of the proposed codes is evaluated and exemplified. The evaluation process contains other metrics: speed and delay, area overhead, power consumption and code redundancy. Chapter 3 contains a proposed scheme to increase security in memory systems against cold-boot attacks. The technique uses data scrambling, hence the chapter begins with a short theoretical background and a review of data scrambling methods. It continues with the proposed solution, which is based on using unique scrambling vectors in an interleaved way, and theoretical performance and efficiency. The chapter ends with evaluation and experimental results for the proposed methodology. Evaluations of area overhead, power consumption and access time are performed in the CACTI simulation tool and on a FPGA development board. Chapter 4 approaches specific types of threats that can prevail in memory systems: simple and differential power or electromagnetic analysis attacks (SPEMA and DPEMA). The chapter begins with short introduction and motivation sections, and continues with a theoretical background about possible threats. In the following section, SPEMA and DPEMA are explained and discussed in detail. Afterwards, the proposed solutions for mitigating SPEMA and DPEMA are exhibited, and ends with evaluation and experimental results. An information leakage function is defined and used in evaluating the security efficiency of the solutions. The implementation costs are assessed with the use of the CACTI simulation tool, with respect to area and delay overhead, and power consumption. The final chapter, 5, contains the conclusions of the work, scientific contributions and future research directions.

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