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Register renaming is an indispensable technique to cope with false data dependencies in out-of-order processors. The critical component for performing register renaming is a register alias table (RAT), which maintains the mappings between architecture and physical registers. Unfortunately, a potential misprediction may seriously slower the processor execution, because new instructions are not allowed to be renamed until the RAT has been restored to the previous correct status. Therefore, a fast RAT recovery is necessary to sustain high performance. As instruction windows size increases, the traditional recovery mechanisms such as using retirement map table and history buffer become too slow. In order to instantly restore RAT from a misprediction, the embedded checkpoint method is introduced but too costly due to creating a large number of checkpoints. In this paper, we propose a selective checkpoint policy which is based on branch confidence and decides when to assign a new checkpoint. Experimental results show that for a 2048-entry large instruction window, our proposal only uses 8 checkpoints to implement fast RAT recovery, reducing the misprediction overhead to just 3% of the ideal model.

A SDRAM like conventional memories can be affected by the occurrence of single event upsets (SEUs) which can lead to serious faults such as single-bit error. In order to cope with this effect of SEUs, a fault-tolerant SDRAM controller is proposed instead of previous approaches that required modifications to the internal structure of the SDRAM itself. For one thing, an optimized encoder and decoder based the (40, 32) Hamming code are integrated to eliminate the problem of single-bit error. Moreover, in the context of error correction, a write request shift register chain is adopted to prefetch the subsequence write requests, and simultaneously a data correction shift register chain is applied to hide the delay of write-back into the following accesses. Besides, with the dynamic combination of two chains, a reconfigurable new chain can be generated to achieve the goal that the burst read data, corrected data and requested write data can be issued seamlessly. Simulation results show that, the optimized encoder and decoder reduce 16.45% area overhead with the slight delay, and the proposed structure could also reduce 11.2% execution time of the test program.