Novel Hermetic Wafer-Level-Packaging Technology using Low-Temperature Passivation

Abstract

In the past decade wafer level packaging (WLP) has been proven to be a very competitive solution regarding performance, miniaturization and costs for a wide range of applications. However, they are up to now not matching the performance of hermetically sealed Glass or Glass-to-MetalSeal packages, esp. when considering application in extreme environment. In this paper a novel packaging technology is proposed, allowing hermetic passivation and encapsulation of microelectronic devices on wafer-level. This technology combines the unique properties of microstructuring of glass on silicon process [1] with the capabilities of a wafer-level packaging technology using Silicon-Via-Contacts [2]. This new processing technology is enabling hermetic encapsulation of devices on wafer-level comprising an unique, cost effective passivation process performed at temperatures below 120°C. Wafer-Level-Packaging and Redistribution using PolymerMost of the successful wafer-level-packaging technologies introduced in the past [3,4] are using polymers as dielectric material for the passivation of microelectronic elements as well as electrical insulation of the device and the redistribution leads of the package. A broad class of materials have been developed ranging from epoxy-based materials and spin-on polymers to polyimids and BCB.Acceptable microstructuring results can be achieved with those materials by plasma etching using a photo-resist mask or by choosing a class of intrinsic photosensitive passivation polymers applying lithography directly.Generally the polymer passivation has to be cured after application to the wafer. The degree of cure of that passivation materials has a strong impact on their passivation properties and therefore on the overall reliability of the packaged electronic devices. If thermal curing is applied, Tg of the polymers is systematically lower than the bake temperature. Standard curing conditions are in the range of 160°C to 380°C for several minutes to hours depending on the polymer material. Sensitive electronic devices i.e. CMOS or analog IC's may suffer significant loss of device performance when exposed to those curing conditions.

Copper / Benzocyclobutene Multi Layer Wiring - A flexible base Technology for Wafer Level Integration of passive Components

“…The glass deposition and structuring technology is formally known as Novolay TM technology from Schott Electronics GmbH and is originally used as passivation or frame material for hermetic wafer level packaging. [16,17] The process, which is fully compatible with the current technology, allows the glass to replace the BCB locally between the electrodes of capacitors. Since the BCB is only replaced locally and still present in the rest of the build-up, the advantages of BCB, like low dielectric loss, low dielectric constant and capability for processing of thick layers, still apply.…”