Novel high-speed bit-parallel multiply accumulate arithmetic architecture

This paper is concerned with the derivation of the relationship that exists between the number truncation in two's complement (TC) arithmetic and the corresponding truncation in signed-binary (SB) arithmetic. The resulting relationship is subsequently exploited and applied to the development of a pair of novel techniques for SB rounding. These techniques are then translated into algorithm suitable for two-level logic implementation. Finally, the resulting algorithms are applied to the design and implementation of a high-speed SB-kernel based TC multiply-accumulate arithmetic architecture.

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Rounding techniques for signed binary arithmetic

Rao

Nowrouzian

Proceedings of 1996 Canadian Conference on Electrical and Computer Engineering

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A novel high-speed parallel multiply-accumulate arithmetic architecture employing modified radix-4 signed-binary recoding

Rao

Nowrouxian²

Proceedings of the 39th Midwest Symposium on Circuits and Systems

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Novel high-speed bit-parallel multiply accumulate arithmetic architecture

Cited by 2 publications

References 5 publications

Rounding techniques for signed binary arithmetic

Rounding techniques for signed binary arithmetic

A novel high-speed parallel multiply-accumulate arithmetic architecture employing modified radix-4 signed-binary recoding

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