Novel Layout Technique for Single-Event Transient Mitigation Using Dummy Transistor

Chen, Jianjun; Chen, Shuming; He, Yuhui; Qin, Jun-Rui; Liang, Bin; Liu, Biwei; Huang, Pengcheng

doi:10.1109/tdmr.2012.2227261

Cited by 58 publications

(32 citation statements)

References 21 publications

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“…Due to the easy look-inside capability, three-dimensional mixed-mode TCAD simulation has been proven to be a useful method to investigate the mechanism of single event charge collection [2,5,9,10,11,12]. In this paper, SET production process is simulated both in a common bulk PMOSFET and in a novel SOI PMOSFET.…”

Section: Device and Simulation Detailsmentioning

confidence: 99%

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Research on single-event transient mechanism in a novel SOI CMOS technology

Zhang

Chen

Chi

et al. 2014

IEICE Electron. Express

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For the first time, compared with common bulk PMOSFETs, single-event transient (SET) mechanism was researched in a novel SOI PMOSFETs using technology computer-aided design mixed-mode numerical (TCAD) simulations. The simulation results showed that, different from the common bulk CMOS technology, diffusion but not bipolar effect is the main mechanism in PMOSFETs fabricated in this novel SOI CMOS technology. The effects of buried oxide (BOX) layer and body tie on SET were also discussed for the PMOSFETs in this technology. The radiation hardened by design (RHBD) layout technique was proposed for further SET mitigation. All of the studies indicated that this novel SOI CMOS technology has the essential advantage for radiation hardened integrated circuit (IC) design.

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Section: Device and Simulation Detailsmentioning

confidence: 99%

“…So SET mitigation in PMOSFET becomes a more important issue. In order to reduce the threat of SET in IC in bulk CMOS process, several efficient radiation hardened by design (RHBD) layout techniques are proposed for SET mitigation [5,7,8,9,10,11]. However, none of these RHBD techniques can significantly reduce SET pulse width.…”

Section: Introductionmentioning

confidence: 99%

Research on single-event transient mechanism in a novel SOI CMOS technology

Zhang

Chen

Chi

et al. 2014

IEICE Electron. Express

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“…The physical mechanisms of charge motion on SETs have been extensively studied in bulk NMOSFETs and triple-well NMOSFETs [4][5][6][7][8][9]. These issues have also been extensively studied in our previous works [10][11][12][13][14]. The process of charge motion on SETs is controlled by drift, diffusion, and amplification effect of a parasitic bipolar transistor.…”

Section: Introductionmentioning

confidence: 99%

The Effect of Deep N+ Well on Single-Event Transient in 65 nm Triple-Well NMOSFET

et al. 2019

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In a triple-well NMOSFET, a deep n+ well (DNW) is buried in the substrate to isolate the substrate noise. The presence of this deep n+ well leads to changes in single-event transient effects compared to bulk NMOSFET. In space, a single cosmic particle can deposit enough charge in the sensitive volume of a semiconductor device to cause a potential change in the transient state, that is, a single-event transient (SET). In this study, a quantitative characterization of the effect of a DNW on a SET in a 65 nm triple-well NMOSFET was performed using heavy ion experiments. Compared with a bulk NMOSFET, the experimental data show that the percentages of average increase of a SET pulse width are 22% (at linear energy transfer (LET) = 37.4 MeV·cm 2 /mg) and 23% (at LET = 22.2 MeV·cm 2 /mg) in a triple-well NMOSFET. This study indicates that a triple-well NMOSFET is more sensitive to a SET, which means that it may not be appropriate for radiation hardened integrated circuit design compared with a bulk NMOSFET.

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“…Recently Zhenyu Wu found that reducing the distance between NMOS transistor and N-well can reduce N-hit SET pulse width [23]. Several works like this use layout optimization methods to maintain the stability of the N-well electronstatic potential and suppress the parasitic bipolar effect [24,25,26,27,28]. Radiation harden by process is another effective method to reduce the damage of single-event effect [9,11].…”

Section: Introductionmentioning

confidence: 99%

Physical mechanism study of N-well doping effects on the single-event transient characteristic of PMOS

Zhao

Peng

Liu

et al. 2019

IEICE Electron. Express

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N-well doping concentration plays an important role in singleevent transient (SET) characteristic of transistors. While adjusting the Nwell doping parameter within a proper range, it has little effect on the basic electrical performance of P-type MOSFET. The physical mechanism of well doping effects on the SET of PMOS is observed. The collapse and recovery of N-well potential, which are the critical factors that influences the SET pulse width, are analyzed by TCAD simulations. The result shows that well doping concentration could affect not only the rate of well potential recover to its equilibrium value, but the potential gradient induced by localized collapse of N-well potential between ion-strike path and source. Energy band analysis is also carried out under the triple well structure, and results show that an increase in well doping concentration will elevate the barrier of reverse-biased P-N junction and therefore cause the accumulation of holes in well, elevating the well potential, and consequently, inhibiting the parasitic bipolar amplification effect.

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Novel Layout Technique for Single-Event Transient Mitigation Using Dummy Transistor

Cited by 58 publications

References 21 publications

Research on single-event transient mechanism in a novel SOI CMOS technology

Research on single-event transient mechanism in a novel SOI CMOS technology

The Effect of Deep N+ Well on Single-Event Transient in 65 nm Triple-Well NMOSFET

Physical mechanism study of N-well doping effects on the single-event transient characteristic of PMOS

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