Novel LDMOS Optimizing Lateral and Vertical Electric Field to Improve Breakdown Voltage by Multi-Ring Technology

Design considerations of a novel Triple Oxide Trench Deep Gate LDMOS to improve self‐heating effect and breakdown voltage

“…Among the semiconductor power devices, lateral doublediffused metal oxide semiconductor field-effect transistors (LDMOS), due to their high performance, have been used in a variety of applications such as high-voltage integrated circuits (HVIC), smart power technologies, and radio frequency (RF) power amplifier applications [1][2][3][4]. Due to the significant advantages of the silicon-on-insulator (SOI) technology, including lower parasitic capacitances, high speed, elimination of latch-up phenomena, high switching speed, superior isolation, and low leakage current, this technology is suitable for the LDMOS devices [5][6][7][8].…”

Improvement of electrostatic discharge current-handling capability for high-voltage multi-finger nLDMOS devices with self-triggered technique

“…Hence, a low ESD level is a serious issue in high-voltage (HV) ICs. Scaling up the device dimension is the conventional method to increase the ESD level, but it is not always effective for metal-oxide semiconductor fieldeffect transistor ESD devices, especially for the HV LDMOS [3][4][5][6][7][8]. The root cause for the scaling limit of ESD robustness of a large-area or a finger-type clamp is the current crowding effect among fingers, and then inducing inhomogeneous triggering of the parasitic bipolar junction transistor (BJT) to cause the non-uniform turn-on issue [1,3].…”

“…The root cause for the scaling limit of ESD robustness of a large-area or a finger-type clamp is the current crowding effect among fingers, and then inducing inhomogeneous triggering of the parasitic bipolar junction transistor (BJT) to cause the non-uniform turn-on issue [1,3]. To overcome this problem, a novel layout arrangement [3][4][5], a new device structure embedding silicon controlled rectifier [6], the gate-coupled technique [9,10], and the substrate-triggered technique [7,8,11] have been proposed for HV LDMOS. The methods in [3][4][5][6] elevate the ESD robustness without occupying additional chip area, while extra ESD detecting circuits and substrate triggering circuits are needed for gate-coupled or substrate-triggered techniques in [7][8][9][10][11].…”

“…To overcome this problem, a novel layout arrangement [3][4][5], a new device structure embedding silicon controlled rectifier [6], the gate-coupled technique [9,10], and the substrate-triggered technique [7,8,11] have been proposed for HV LDMOS. The methods in [3][4][5][6] elevate the ESD robustness without occupying additional chip area, while extra ESD detecting circuits and substrate triggering circuits are needed for gate-coupled or substrate-triggered techniques in [7][8][9][10][11]. Achieving the goal of high ESD current-handling capability without any extra chip area is of course the most candidate method.…”

Wide Bandgap Engineering in Power Transistors Using GaN Windows

“…Power electronic devices based on the semiconductors are among the main topics of research for 50 years. 1 Silicon-based devices show many limitations to answer the increased demand from power switches, 2,3 Gallium nitride (GaN) was the best replace of silicon with wide bandgap structure. GaN has a band gap of 3.4 eV and electron mobility of 1100 cm 2 /V that makes the GaN device the most promising technology for the next generation of power applications.…”