Novel negative Vt shift program disturb phenomena in 2X&amp;#x223C;3X nm NAND flash memory cells

Seo, Soonok; Kim, Hyung Seok; Park, Sung-Kye; Lee, Seokkiu; Aritome, S.; Hong, Sung-Joo

doi:10.1109/irps.2011.5784548

Cited by 8 publications

(4 citation statements)

References 6 publications

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“…Air-gap isolation as well as optimization of channel implant and STI depth uniformity [277] have been suggested as remedies. A related effect has been noted in [278], where a negative V T shift contribution was found and explained in terms of hot-hole injection from the STI edge to the control-gate [279,280]. All this suggests that the detailed leakage mechanisms affecting the boosted channel potential must be studied with extreme care [281].…”

Section: Program and Pass Disturbsmentioning

confidence: 75%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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Abstract:We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field. Particular emphasis is placed on mechanisms developing along the lifetime of the memory array, as opposed to time-zero or technological issues, and the viewpoint is focused on the understanding of the root causes. The impressive amount of published work demonstrates that Flash reliability is a complex yet well-understood field, where nonetheless tighter and tighter constraints are set by device scaling. Three-dimensional NAND have offset the traditional scaling scenario, leading to an improvement in performance and reliability while raising new issues to be dealt with, determined by the newer and more complex cell and array architectures as well as operation modes. A thorough understanding of the complex phenomena involved in the operation and reliability of NAND cells remains vital for the development of future technology nodes.

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Section: Program and Pass Disturbsmentioning

confidence: 75%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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“…The NAND Flash technology scaling has introduced additional disturbance mechanisms affecting the array reliability: the cell-to-cell interference [63], [64], [65], [66] and the Gate Induced Drain Leakage (GIDL) [67], [68]. The former issue is mainly caused by the FG coupling due to parasitic capacitances between cells, thus it is greatly affected by cell scaling, and is well known to widen the V T distributions by producing read errors.…”

Section: B Reliability Effectsmentioning

confidence: 99%

Solid-State Drives: Memory Driven Design Methodologies for Optimal Performance

et al. 2017

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Solid-state drives (SSDs) faced an astonishing development in the last few years, becoming the cornerstone to new paradigms and markets of the information technology, such as cloud computing and big data centers. So far, the SSD design approach has focused on the optimization of the Flash translation layer, the firmware devoted to fulfill the compatibility with traditional hard-disk drives. For hyperscaled SSDs this strategy is no longer valid since their performance and reliability are strictly linked to that of the NAND Flash memories that constitute the storage medium, in particular when the multilevel cell paradigm is considered. For this reason, the design flow must follow a bottom-up approach that, starting from an accurate knowledge of the time and use dependent reliability of the NAND Flash memories, selects the most appropriate error correction strategy to extend the SSD lifetime while reducing its performance degradation. Then, the design flow moves to that of the SSD controller and of the interface toward the host where the application is running. This paper will thoroughly discuss this bottom-up approach, and finally, it will show how it is possible to leverage new approaches, such as the software-defined storage system that, by exploiting a hardware/software codesign of the SSD controller architecture and of the host application, will be able to revolutionize the traditional computer/memory interaction

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“…However, to implement this structure, there will be always uncertainty in the cell gate length and WL gap owing to process variations such as gate line edge roughness (LER), etch slope variation, and lithography resolution-induced variation, for example. [21][22][23][24][25][26][27] Therefore, this structure has an ONcell current and threshold voltage sensitive to cell gate length fluctuation, which might affect the threshold voltage distribution and memory performance adversely.…”

Section: Introductionmentioning

confidence: 99%

Variation of Threshold Voltage and ON-Cell Current Caused by Cell Gate Length Fluctuation in Virtual Source/Drain NAND Flash Memory

Kim

Park

et al. 2012

Jpn. J. Appl. Phys.

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Tunnelling spectroscopy with simultaneous transmission electron microscopy (TEM) was applied to an Fe-MgO composite film in which the Fe nano-particles were sandwiched by two thin MgO layers and nanometer-scale double-barrier tunnel junctions were formed. Using a movable needle-shaped electrode, nano-regions were selected and the geometry of the particle system was deformed. The real-time and simultaneous experiments of the deformation, the tunnel measurement and the TEM observation made it possible to confirm the condition under which the Coulomb staircase clearly appears. The measured staircase period corresponded approximately to the value estimated from the geometry observed by TEM. Thus, the feasibility of this method was verified.

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Novel negative Vt shift program disturb phenomena in 2X∼3X nm NAND flash memory cells

Cited by 8 publications

References 6 publications

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

Solid-State Drives: Memory Driven Design Methodologies for Optimal Performance

Variation of Threshold Voltage and ON-Cell Current Caused by Cell Gate Length Fluctuation in Virtual Source/Drain NAND Flash Memory

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