Novel operation schemes to improve device reliability in a localized trapping storage SONOS-type flash memory

Yeh, Chih-Ting; Tsai, Wen-Jer; Lu, Tsung-Chien; Chen, H.Y.; Lai, Hang–Chin; Zous, N.K.; Liao, Yi-Ying; You, Gao; Cho, S.K.; Liu, C.C.; Hsu, Feng-Mao; Huang, L.; Chiang, W.S.; Liu, C.J.; Cheng, C. C.; Chou, Ming Yueh; Chen, C.H.; Wang, Tahui; Ting, W.; Pan, S.C.; Ku, J.; Lu, Chih‐Yuan

doi:10.1109/iedm.2003.1269204

Cited by 11 publications

(6 citation statements)

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“…This produces a microscopically stable trapped charge configuration. Hence, soft erase serves an "electrical annealing" [2,7,8,9]. The results from V G -accelerated and baking (150 0 C) retention tests are shown in Figs.…”

Section: The Effect Of Soft Erase On Retentionmentioning

confidence: 98%

“…The retention degradation mechanism of NBit/NROM has been studied extensively recently [4][5][6][7][8][9][10]. However, so far there is no consensus about the root cause of charge loss after P/E cycling.…”

Section: Introductionmentioning

confidence: 99%

“…This prevents the direct tunneling of stored charge but yet allows BBHH injection for erase operation, with good data retention. However, hot-hole erase causes considerable reliability concerns [5][6][7][8][9]. The most important issue is the retention degradation of the highVt programmed state after P/E cycling.…”

Section: Introductionmentioning

confidence: 99%

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Study of Charge Loss Mechanism of SONOS-Type Devices using Hot-Hole Erase and Methods to Improve the Charge Retention

Lue

Hsiao

Shih

et al. 2006

2006 IEEE International Reliability Physics Symposium Proceedings

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The retention degradation mechanism of NBit/NROM [1] is examined by several unique techniques that promise unequivocal results. The in-situ 150 0 C electrical testing is used to examine the electron/hole stability. We find no discernable electron/hole lateral migration in the nitride. Next, we apply the refill [2] and soft erase [2] methods with various electrical conditions to study the charge loss mechanism. We demonstrate that the refill method can electrically modify the trap energy spectrum, and soft erase method can recover the damages induced by hothole stressing. The experimental results show that the vertical charge loss measured by Vg-accelerated retention test at 25 0 C is highly correlated to the charge loss measured at 150 0 C baking. Since refill and soft erase techniques alter the trapped electron energy spectrum and the excess-hole distribution differently, these correlations strongly support the vertical charge loss model. Finally, the retention is greatly improved by the refill and soft erase methods and further improvement may be expected by engineering the nitride traps.

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Section: The Effect Of Soft Erase On Retentionmentioning

confidence: 98%

Section: Introductionmentioning

confidence: 99%

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Study of Charge Loss Mechanism of SONOS-Type Devices using Hot-Hole Erase and Methods to Improve the Charge Retention

Lue

Hsiao

Shih

et al. 2006

2006 IEEE International Reliability Physics Symposium Proceedings

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“…The standard Incremental Step Pulse Program (ISPP) [16] algorithm and the enhanced one to reduce the charge loss suffered by CT-NAND, hereafter denoted as Recovery (REC) [15], [18], are depicted in Fig. 5.…”

Section: B Program Algorithmsmentioning

confidence: 99%

“…Since the high BER in CT-NAND is mainly due to charge loss in shallow traps, the straightforward solution is to design program algorithms able to stabilize the trapped charge. The enhanced program algorithms presented in literature [11], [15] will result in a programming time increase compared to the standard program algorithms [16], but their advantages in terms of reliability and overall QoS are terrific.…”

Section: Introductionmentioning

confidence: 99%

Quality-of-Service Implications of Enhanced Program Algorithms for Charge-Trapping NAND in Future Solid-State Drives

Grossi

Zuolo

Restuccia

et al. 2015

IEEE Trans. Device Mater. Relib.

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3D-NAND memories based on Charge Trapping (CT) technology represent the most promising solution for hyperscaled Solid State Drives (SSD). However, the intrinsic low reliability offered by that storage medium leads to a high number of errors requiring an extensive use of complex Error Correction Codes (ECC) and advanced read algorithms such as Read Retry. This materializes in an overall SSD's Quality of Service (QoS) reduction. In order to limit the errors number, enhanced program algorithms able to improve the reliability figures of CT memories have been introduced. In this work, the impact of such program algorithms combined with Read Retry and ECC is experimentally characterized on CT-NAND arrays. The results are then exploited for co-simulations at system level, assessing reliability, performance and QoS of future SSD integrating CTbased memories.

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Coding scheme for 3D vertical flash memory

Kim

Mateescu

Song

et al. 2015

2015 IEEE International Conference on Communications (ICC)

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Abstract-Recently introduced 3D vertical flash memory is expected to be a disruptive technology since it overcomes scaling challenges of conventional 2D planar flash memory by stacking up cells in the vertical direction. However, 3D vertical flash memory suffers from a new problem known as fast detrapping, which is a rapid charge loss problem. In this paper, we propose a scheme to compensate the effect of fast detrapping by intentional inter-cell interference (ICI). In order to properly control the intentional ICI, our scheme relies on a coding technique that incorporates the side information of fast detrapping during the encoding stage. This technique is closely connected to the well-known problem of coding in a memory with defective cells. Numerical results show that the proposed scheme can effectively address the problem of fast detrapping.

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Novel operation schemes to improve device reliability in a localized trapping storage SONOS-type flash memory

Cited by 11 publications

References 1 publication

Study of Charge Loss Mechanism of SONOS-Type Devices using Hot-Hole Erase and Methods to Improve the Charge Retention

Study of Charge Loss Mechanism of SONOS-Type Devices using Hot-Hole Erase and Methods to Improve the Charge Retention

Quality-of-Service Implications of Enhanced Program Algorithms for Charge-Trapping NAND in Future Solid-State Drives

Coding scheme for 3D vertical flash memory

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