Novel packaging with rematable spring interconnect chips for MCM

A package demonstration with solder free compliant flexible interconnects

“…The silicon IC has incorporated four corner etch pits each housing a precision spacer glass ball. In previous work, matching pits in another substrate were used to enable very precise 3D alignment of chips (with tolerances below +/-2 μm) while only requiring a coarse (>50 μm) alignment accuracy from assembly tools [1,13]. In this work, the ceramic and organic substrates do not have matching pits, so the balls are used only to establish an accurate gap.…”

“…Figure 10 shows completed finished package assemblies. Understandably the adhesive permanently locks the chip down while in order to benefit from the micro-spring interconnect rework capability one would need to deploy a clamping mechanism facilitating both package assembly and des-assembly similar to that shown in [1]. Adhesive has been utilized in this work in order to secure the chip on the substrate to expedite the demonstration of the spring interconnect operation and performance.…”

“…Previously, we have realized micro-spring prototypes that meet the stringent electrical and mechanical demands of a typical modern, high-performance microprocessor package; each spring provides <100 mΩ per connection and >30 μm of compliance; spring reliability was also confirmed under 0-100°C temperature cycling, 85/85 temperature humidity bias, and a high-current soak [1][2].…”

“…They also provide rematable connections to enable a reusable, reworkable MCM platform where an ability to separate non-functional and functional die, i.e. identifying known good die (KGD), is key to enhancing assembly yield.Previously, we have realized micro-spring prototypes that meet the stringent electrical and mechanical demands of a typical modern, high-performance microprocessor package; each spring provides <100 mΩ per connection and >30 μm of compliance; spring reliability was also confirmed under 0-100°C temperature cycling, 85/85 temperature humidity bias, and a high-current soak [1][2]. …”

Integration and Packaging of a Macrochip With Silicon Nanophotonic Links

“…Our approach is based on stressengineered spring interconnects that can improve testing, remateability, and conductive connection tolerance for the power delivery infrastructure deployed within large chip array packages, such as the macrochip [16], [17]. Further, as I/O pad size and pitch reduce over the course of new technology generations, our spring-based interconnect approach can be miniaturized to keep pace owing to their lithographic definition.…”