Integration and Packaging of a Macrochip With Silicon Nanophotonic Links

Abstract

Abstract-The technologies associated with integration and packaging have a significant impact on the overall system. In this paper, we review a silicon photonic "macrochip" system and its associated packaging that will allow dense wavelengthdivision multiplexed optical links to be intimately integrated and co-manufactured with the switching electronics. For this to happen, we anticipate a number of integration and packaging advances.

Chip-to-chip interconnect integration technologies

“…2(c)) has also been widely researched as it allows a significantly higher bandwidth density using fine pitch silicon waveguides [1,4] and WDM. Assuming a waveguide pitch of 10 µm [12] with 8 WDM channels and each channel operating at 10 Gb/s, the bandwidth density achievable using nanophotonics integration on interposer is ∼8 Tb/s/mm.…”

“…However, again, the EPB expensed in electrical to optical conversion and vice versa, along with the laser efficiency dictates the interconnect length after which utilization of nanophotonic interconnect becomes feasible in terms of power dissipation. Oracle's macrochip [1,13] architectures aims to leverage silicon nanophotonic integration to form a large passive grid of silicon waveguides embedded in a silicon lattice; the LSI chips (processors, RAM modules etc.) are connected to the lattice via a 'bridge' chip that converts the electrical signal to optical and couples it into the waveguide network [13,14].…”

“…Consequently, there are significant ongoing research efforts aiming to overcome this hurdle. While building reticle-sized chips can partially solve the problem, it is not economically feasible [1]. Recent advances in 2.5D [2,3] packaging as well as silicon interposer-level optical interconnects [4] have allowed high-bandwidth communication between chips (or stack of chips) on interposers.…”

Design considerations for a 33mW, 12.5 Gbps × 8 channel silicon photonic transmitter array

“…As discussed extensively elsewhere, our photonic systems focus on hybrid integration of CMOS circuits and SOI optical devices, because this enables us to optimize each platform for best performance [7], [9], [10]. An example of this optimization is a silicon under-etch around and under the rings, which significantly increases thermal impedance from the ring to the surrounding material [11], [12].…”

Large-scale, surface tension assisted Ball-in-Pit self population for chip-to-chip passive alignment

“…It has been shown that 10µm or less vertical separation between two couplers is required for high fidelity and low bit-error rate PxC [9]. Overall, the Ball-in-Pit fabrication and assembly process being developed at Oracle Labs has the promise of a low-cost approach for integration and critical alignment in a multi-chip system [10]. However, populating etched pits with balls is presently performed manually by a technician using vacuum pick-up tools and is therefore not feasible for large-scale i.e.…”