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Using low parasitic microsolder bumping, we hybrid integrated efficient photonic devices from different platforms with advanced 40 nm CMOS VLSI circuits to build ultra-low power silicon photonic transmitters and receivers for potential applications in high performance inter/intra-chip interconnects. We used a depletion racetrack ring modulator with improved electro-optic efficiency to allow stepper optical photo lithography for reduced fabrication complexity. Integrated with a low power cascode 2 V CMOS driver, the hybrid silicon photonic transmitter achieved better than 7 dB extinction ratio for 10 Gbps operation with a record low power consumption of 1.35 mW. A received power penalty of about 1 dB was measured for a BER of 10(-12) compared to an off-the-shelf lightwave LiNOb3 transmitter, which comes mostly from the non-perfect extinction ratio. Similarly, a Ge waveguide detector fabricated using 130 nm SOI CMOS process was integrated with low power VLSI circuits using hybrid bonding. The all CMOS hybrid silicon photonic receiver achieved sensitivity of -17 dBm for a BER of 10(-12) at 10 Gbps, consuming an ultra-low power of 3.95 mW (or 395 fJ/bit in energy efficiency). The scalable hybrid integration enables continued photonic device improvements by leveraging advanced CMOS technologies with maximum flexibility, which is critical for developing ultra-low power high performance photonic interconnects for future computing systems.

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We describe transmitter and receiver circuits for a 10-Gbps single-ended optical link in a 40-nm CMOS technology. The circuits are bonded using low-parasitic micro-solder bumps to silicon photonic devices on a 130-nm SOI platform. The transmitter drives oval resonant ring modulators with a 2-V swing and employs static thermal tuners to compensate for optical device process variations. The receiver is based on a transimpedance amplifier (TIA) with 4-k gain and designed for an input power of 15 dBm, a photodiode responsivity of 0.7 A/W, and an input extinction ratio of 6 dB. It employs a pair of interleaved clocked sense-amplifiers for voltage slicing and uses a DLL with phase adjustment for centering the clock in the data eye. Periodic calibration allows for adjustment of both voltage and timing margins. At 10 Gbps, the transmitter extinction ratio exceeds 7 dB and, excluding thermal tuning and laser power, it consumes 1.35 mW. At the same datarate, the receiver consumes 3.95 mW. On-chip PRBS generators and checkers with sequences confirm operation at a BER better than .

We report the first sub-picojoule per bit (400fJ/bit) operation of a silicon modulator intimately integrated with a driver circuit and embedded in a clocked digital transmitter. We show a wall-plug power efficiency below 400microW/Gbps for a 130nm SOI CMOS carrier-depletion ring modulator flip-chip integrated to a 90nm bulk Si CMOS driver circuit. We also demonstrate stable error-free transmission of over 1.5 petabits of data at 5Gbps over 3.5 days using the integrated modulator without closed-loop ring resonance tuning. Small signal measurements of the CMOS ring modulator, sans circuit, showed a 3dB bandwidth in excess of 15GHz at 1V of reverse bias, indicating that further increases in transmission rate and reductions of energy-per-bit is possible while retaining compatibility with CMOS drive voltages.