Ultra-efficient 10Gb/s hybrid integrated silicon photonic transmitter and receiver

Abstract

Using low parasitic microsolder bumping, we hybrid integrated efficient photonic devices from different platforms with advanced 40 nm CMOS VLSI circuits to build ultra-low power silicon photonic transmitters and receivers for potential applications in high performance inter/intra-chip interconnects. We used a depletion racetrack ring modulator with improved electro-optic efficiency to allow stepper optical photo lithography for reduced fabrication complexity. Integrated with a low power cascode 2 V CMOS driver, the hybrid silicon photonic transmitter achieved better than 7 dB extinction ratio for 10 Gbps operation with a record low power consumption of 1.35 mW. A received power penalty of about 1 dB was measured for a BER of 10(-12) compared to an off-the-shelf lightwave LiNOb3 transmitter, which comes mostly from the non-perfect extinction ratio. Similarly, a Ge waveguide detector fabricated using 130 nm SOI CMOS process was integrated with low power VLSI circuits using hybrid bonding. The all CMOS hybrid silicon photonic receiver achieved sensitivity of -17 dBm for a BER of 10(-12) at 10 Gbps, consuming an ultra-low power of 3.95 mW (or 395 fJ/bit in energy efficiency). The scalable hybrid integration enables continued photonic device improvements by leveraging advanced CMOS technologies with maximum flexibility, which is critical for developing ultra-low power high performance photonic interconnects for future computing systems.

Sub-fF-Capacitance Photonic-Crystal Photodetector Towards fJ/bit On-Chip Receiver

“…These receivers support a high conversion efficiency and large bandwidth thanks to the integrated amplifiers. However, it should be noted that such amplifiers also consume a huge amount of electric power (several mW) [5], [6], and this dominates the overall power consumption. To exceed these conventional receivers with resistor-loaded receiver in terms of EBP, C should be lower than 1 fF.…”

“…A photoreceiver will be a critical device because of its large energy consumption. This mainly originates from the need to use a trans-impedance amplifier (TIA) and some voltage amplifiers for a conventional receiver circuit, which incurs an energy cost of hundred fJ/bit and requires an area of more than 10 4 μm 2 [4]- [6]. Therefore, this will constitute a significant bottleneck when implemented for dense on-chip communication [7].…”

Photonic-crystal nano-photodetector with ultrasmall capacitance for on-chip light-to-voltage conversion without an amplifier

“…To this end, onchip/off-chip optical communication has been extensively studied [1][2][3][4]. For more sophisticated data processing in an on-chip application beyond simple optical communication, a photonicnetwork-on-chip (PhNoC) architecture, which includes many integrated nanophotonic devices that can manage high-speed optical signals, has also been discussed [1,5].…”

“…Photoreceivers generally consist of a photodetector (PD) and a trans-impedance amplifier (TIA) to generate sufficient voltage to drive the subsequent electronic circuits, and they are often fully integrated at the CMOS level for short-range optical interconnection [6,7]. However, even with a recent CMOS-integrated PD-TIA, the power consumption of several milliwatts dominates the total power of the system [2,3]. This amounts to a subpicojoule/bit level energy cost if we assume a signal bit rate of 10 Gbit/s, and concern is growing that this situation will constitute a significant bottleneck when establishing chip-com photonic networks [4].…”

25-Gb/s Optical Transmitter with Si Ring Modulator and CMOS Driver

“…Si photonic systems can be realized either in the hybrid or monolithic manner as each offers its own advantages and disadvantages [7,8]. Monolithic integration minimizes parasitic components but requires complicated processing technology in order to realize both photonic devices and electronic circuits on the same wafer.…”