Novel Quantum Dot Gate FETs and Nonvolatile Memories Using Lattice-Matched II–VI Gate Insulators

Abstract

This paper presents the successful use of ZnS/ZnMgS and other II-VI layers (lattice-matched or pseudomorphic) as high-k gate dielectrics in the fabrication of quantum dot (QD) gate Si field-effect transistors (FETs) and nonvolatile memory structures. Quantum dot gate FETs and nonvolatile memories have been fabricated in two basic configurations: (1) monodispersed cladded Ge nanocrystals (e.g., GeO x -cladded-Ge quantum dots) site-specifically selfassembled over the lattice-matched ZnMgS gate insulator in the channel region, and (2) ZnTe-ZnMgTe quantum dots formed by self-organization, using metalorganic chemical vapor-phase deposition (MOCVD), on ZnS-ZnMgS gate insulator layers grown epitaxially on Si substrates. Self-assembled GeO xcladded Ge QD gate FETs, exhibiting three-state behavior, are also described. Preliminary results on InGaAs-on-InP FETs, using ZnMgSeTe/ZnSe gate insulator layers, are presented.

Sequential Logic Circuits Using Spatial Wavefunction Switched (SWS) FETs

“…The Inverter design uses two n-channel SWSFETs [1]. The twin source and drain configuration is operated in such a way that either of the two wells is chosen according to the applied input voltage.…”

“…The need for high speed, power efficient and compact integrated circuits has led to the invention of novel quantum devices like quantum dot gate FETs (QDGFETs), quantum dot channel FETs (QDCFETs) [1,2] and spatial wavefunction-switched FETs (SWSFETs) [3]. These devices use semiconductor materials like Ge, InGaAs and high-k lattice matched layers as gate insulator which reduces the leakage current as opposed to the regular SiO 2 gate oxide in the sub-12-nm regime.…”

Nonvolatile Memories Using Quantum Dot (QD) Floating Gates Assembled on II–VI Tunnel Insulators

“…The next layer is identical to the first ZnS layer, with 1-min growth of ZnS at 360°C with 35 mW/cm 2 of UV irradiation using DMSe and DMZn as sources, and finally a quick ZnSe cap for 30 s of growth at 360°C with UV irradiation. 1 The first layer in the tunneling insulator stack is the ZnS buffer. This was followed by introducing Mg for the second layer of ZnMgS serving as the primary high-j, high-energy barrier gate insulator.…”

“…The energy band diagram calculations involve self-consistent solution of Poisson and Schrödinger equations, as well as tunneling rate formulation. 1 Here, the carrier concentration is shown in the inversion channel as well as in the first layer of quantum dots (QD-1). The electron transfer from the inversion layer to quantum dots is determined by the II-VI gate insulators and the cladding on the quantum dots.…”

“…1 The motivation behind using II-VI lattice-matched gate dielectrics is twofold: (1) to reduce interface states and their adverse impact on threshold voltage, in particular its variation from device to device in sub-22-nm structures, and (2) to utilize the higher dielectric constant of ZnS/ZnMgS with respect to SiO 2 . Quantum dot nonvolatile memories were first reported by Tiwari et al, 2 where nonuniform uncladded nanocrystalline dots of Si were deposited.…”