This paper presents the observation of intermediate state in the quantum dot gate field-effect transistors (QDGFETs) in silicon-on-insulator (SOI) substrate. Silicon dioxide (SiO 2)-cladded silicon (Si) quantum dots (QDs) are site-specifically selfassembled on the top of SiO 2 tunnel gate insulator on SOI substrates. Charge carrier tunnelling from the inversion channel to the QD layers on top of the gate insulator is responsible for the generation of intermediate state. Charge tunnelling is also verified by the C-V characteristics of the MOS device having same insulator structure as the gate region of the QDGFET. Considering the transfer of charge carriers from the inversion channel to two layers of SiO 2-cladded Si QDs, a model based on self-consistent solution of Schrödinger and Poisson equations, is also presented, to explain the generation of intermediate state.

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This paper presents the implementation of a novel InGaAs field-effect transistor (FET), using a ZnSe-ZnS-ZnMgS-ZnS stacked gate insulator, in a spatial wavefunction-switched (SWS) structural configuration. Unlike conventional FETs, SWS devices comprise two or more asymmetric coupled quantum wells (QWs). This feature enables carrier transfer vertically from one quantum well to another or laterally to the wells of adjacent SWS-FET devices by manipulation of the gate voltages (V g ). Observation of an extra peak (near both accumulation and inversion regions) in the capacitance-voltage data in an InGaAs-AlInAs two-quantum-well SWS structure is presented as evidence of spatial switching. The peaks are attributed to the appearance of carriers first in the lower well and subsequently their transfer to the upper well as the gate voltage is increased. The electrical characteristics of a fabricated SWS InGaAs FET are also presented along with simulations of capacitance-voltage (C-V) behavior, showing the effect of wavefunction switching between wells. Finally, logic operations involving simultaneous processing of multiple bits in a device, using coded spatial location of carriers in quantum well channels, are also described.

This paper presents the successful use of ZnS/ZnMgS and other II-VI layers (lattice-matched or pseudomorphic) as high-k gate dielectrics in the fabrication of quantum dot (QD) gate Si field-effect transistors (FETs) and nonvolatile memory structures. Quantum dot gate FETs and nonvolatile memories have been fabricated in two basic configurations: (1) monodispersed cladded Ge nanocrystals (e.g., GeO x -cladded-Ge quantum dots) site-specifically selfassembled over the lattice-matched ZnMgS gate insulator in the channel region, and (2) ZnTe-ZnMgTe quantum dots formed by self-organization, using metalorganic chemical vapor-phase deposition (MOCVD), on ZnS-ZnMgS gate insulator layers grown epitaxially on Si substrates. Self-assembled GeO xcladded Ge QD gate FETs, exhibiting three-state behavior, are also described. Preliminary results on InGaAs-on-InP FETs, using ZnMgSeTe/ZnSe gate insulator layers, are presented.

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