Novel Silicon On Insulator Metal Oxide Semiconductor Field Effect Transistors with Buried Back Gate

Oh, Hyuckjae; Choi, Hoon; Sakaguchi, Takeshi; Shim, JeoungChill; Kurino, Hiroyuki; Koyanagi, Mitsumasa

doi:10.1143/jjap.43.2140

Cited by 7 publications

(4 citation statements)

References 5 publications

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“…4) The bootstrap voltage has been changed from 1.2 to 1.5 V because of the simulated device model limitation. 12) From Fig. 7, it is shown that the write threshold bit line voltage was decreased from 17 to 28% under the 1.5 V bootstrap voltage.…”

Section: Simulation Results and Discussionmentioning

confidence: 95%

“…The proposed writing scheme has been confirmed by circuit simulation using 0.1 mm silicon on insulator complementary metal-oxide-semiconductor (SOI CMOS) technology. 12) This SOI CMOS has a back gate to vary its threshold voltage; therefore. it is effective for low-power application.…”

Section: Simulation Results and Discussionmentioning

confidence: 99%

“…it is effective for low-power application. 12) Simulation parameters are listed in Table I. The proposed reading and writing spin-transfer MTJ model has been embedded into a commercial simulator.…”

Section: Simulation Results and Discussionmentioning

confidence: 99%

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Low Power Spin-Transfer Magnetoresistive Random Access Memory Writing Scheme with Selective Word Line Bootstrap

Sugimura¹,

Sakaguchi²,

Fukushima³

et al. 2007

jjap

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We describe a new writing scheme with a selective word line bootstrap for spin-transfer magnetoresistive random access memory (MRAM). Applying spin-transfer switching to MRAM, its writing power consumption decreases and its memory cell area is also reduced. However, during write operation, the required bit line cramp voltage for stored data switching depends on the value of stored data, magnetic tunnel junction (MTJ) characteristics, and switching current direction. Therefore, the bit line voltage must be optimized to minimize the power consumption. With the proposed scheme, word line voltage is varied according to the value of writing data in order to decrease the threshold bit line voltage. Furthermore, the spin-transfer MRAM resistance model with reading and writing operations was successfully implemented for the circuit simulation. From the simulation results, it was found that writing threshold bit line bias during writing operation can decrease from 17 to 28% with the proposed selective bootstrap. Also, more than 25% of the cell transistor gate width can be decreased. This result shows that the proposed writing scheme is effective in reducing power consumption, and can also reduce the MRAM cell area.

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Section: Simulation Results and Discussionmentioning

confidence: 95%

Section: Simulation Results and Discussionmentioning

confidence: 99%

See 1 more Smart Citation

Low Power Spin-Transfer Magnetoresistive Random Access Memory Writing Scheme with Selective Word Line Bootstrap

Sugimura¹,

Sakaguchi²,

Fukushima³

et al. 2007

jjap

Self Cite

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show abstract

“…Therefore, FD SOI-MOSFET with a back gate has been extensively researched. [2][3][4] However, there are still many difficulties in terms of parasitic capacitance and the low controllability of threshold voltage because of substrate depletion and the low conductivity of the back gate region in a silicon-based ion-implanted back gate. These difficulties are also observed in the fabrication process of the device because back gate formation must be carefully optimized to reduce the influence of device characteristics causing diffusion in the SOI wafer due to the buried oxide (BOX) interface effects.…”

Section: Introductionmentioning

confidence: 99%

Characteristics of Silicon-on-Low k Insulator Metal Oxide Semiconductor Field Effect Transistor with Metal Back Gate

Yamada¹,

Oh²,

Sakaguchi³

et al. 2006

jjap

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We proposed a silicon-on-low k insulator (SOLK) metal oxide semiconductor field effect transistor (MOSFET) with a metal back gate for high-speed and ultralow power devices. In this work, Benzocyclobutene (BCB) and tetramethyl ammonium hydroxide (TMAH) were employed to fabricate SOLK Devices without damaging the transistor channels. We successfully fabricated the proposed submicron fully depleted (FD) SOLK MOSFETs with a metal back gate. The process technologies and electrical properties of SOLK MOSFETs were introduced in detail. Furthermore, threshold voltage shift was obtained at 55 mV/V using a NMOSFET and at 35 mV/V using a PMOSFET and drain current characteristics are enhanced by the back gate bias.

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Silicon on thin BOX: a new paradigm of the CMOSFET for low-power and high-performance application featuring wide-range back-bias control

Tsuchiya

Horiuchi

Kimura

et al.

IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004.

132

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Novel Silicon On Insulator Metal Oxide Semiconductor Field Effect Transistors with Buried Back Gate

Cited by 7 publications

References 5 publications

Low Power Spin-Transfer Magnetoresistive Random Access Memory Writing Scheme with Selective Word Line Bootstrap

Low Power Spin-Transfer Magnetoresistive Random Access Memory Writing Scheme with Selective Word Line Bootstrap

Characteristics of Silicon-on-Low k Insulator Metal Oxide Semiconductor Field Effect Transistor with Metal Back Gate

Silicon on thin BOX: a new paradigm of the CMOSFET for low-power and high-performance application featuring wide-range back-bias control

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