Novel Simulink Blockset for Image Processing Codesign

Roozmeh

ACM Trans. Embed. Comput. Syst.

2016

Model-based hardware design allows one to map a single model to multiple hardware and/or software architectures, essentially eliminating one of the major limitations of manual coding in C or RTL. Model-based design for hardware implementation has traditionally offered a limited set of micro-architectures, which are typically suitable only for some application scenarios. In this paper we illustrate how DSP algorithms can be modeled as flexible intellectual property blocks, to be used within the popular Simulink model-based design environment. These blocks are written in C, and are designed for both functional simulation and hardware implementation, including architectural design space exploration and hardware implementation through high level synthesis. A key advantage of our modeling approach is that the very same bit-accurate model is used for simulation and high-level synthesis. To prove the feasibility of our proposed approach, we modeled an FFT algorithm and synthesized it for different DSP applications with very different performance and cost requirements. We also implemented a high level synthesis IP generator that can generate flexible FFT HLS-IP blocks that can be mapped to multiple micro/macro-architectures, to enable design space exploration as well as being used for functional simulation in the Simulink environment.

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Section: Related Workmentioning

confidence: 99%

Designing Parameterizable Hardware IPs in a Model-Based Design Environment for High-Level Synthesis

Roozmeh

ACM Trans. Embed. Comput. Syst.

2016

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“…In [9] a Simulink image processing blockset is presented for hardware/software codesign, using Xilinx System Generator at the backend for hardware generation. In [10] an ESL design tool is presented that can do automatic design space exploration starting from behavioral SystemC models.…”

Section: Related Workmentioning

confidence: 99%

Simulink-based hardware/software trade-off analysis technique

Sayyah

2011 IEEE Jordan Conference on Applied Electrical Engineering and Computing Technologies (AEECT)

2011

Fast analysis of hardware/software trade-offs for cost, performance and power-constrained embedded systems is a key to reduce the time to market and at the same time improve the quality of results. However, this analysis must also be close to the final results of the detailed HW and SW implementation in order to lead to an optimal solution. This requires the use of compilation (for SW) and synthesis (for HW) techniques that ensure the existence of a solution with the estimated cost, and are not too far from what will later be achieved by manual optimization and detailed design.We start from a realistic application domain, namely soundtriggered wireless security cameras, and we show in detail how one can start from an algorithm modeled and validated using Simulink, and using commercial state-of-the-art tools explore various possible hardware and software implementations for the frequency based audio detection front end, with respect to the overall design constraints and goals. We show how rapid estimations of the various aspects of the cost function can be obtained quickly, using directly the C code generated from Simulink, with a few manual refinements in order to increase the efficiency of both software and hardware implementations and bring them closer to the final optimized implementation. We report results showing different points in the design space. The results that we obtained are close to manual hand optimized implementations for both HW and SW, showing that the approach is useful for trade-off analysis in a very short time, and that further manual optimizations can quickly lead to the best implementation.

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Design space exploration and synthesis for digital signal processing algorithms from Simulink models

2013 8th IEEE Design and Test Symposium

2013