Novel Superjunction LDMOS (&gt;950 V) With a Thin Layer SOI

Zhang, Wentong; Zhan, Zhenya; Yu, Yang; Cheng, Shikang; Gu, Yu; Zhang, Sen; Luo, Xiaorong; Li, Zehong; Qiao, Ming; Li, Zhaoji; Zhang, Chao

doi:10.1109/led.2017.2751571

Cited by 42 publications

(18 citation statements)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The investigated SJ-MGFETs have a complex 3-D design permitted by a non-planar technology [12] with an embedded deep trench gate and heavily doped alternating U-shaped n-type and p-type doping pillars forming a SJ drift region length of L drif t with a pillar height of d n−pillar [11]. The whole transistor structure is grown on a buried oxide layer to mitigate the effect of substrate-assisted depletion (SAD) [13,14,15]. This silicon-on-insulator (SOI) SJ-MGFET has a 1 µm gate length (L gate ) with a 0.5 µm channel (L ch ) length underneath.…”

Section: Device Structure Of the Sj-mgfetmentioning

confidence: 99%

Scaling and optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub–50 V applications

Adenekan

Holland

Kálna

2019

Microelectronics Reliability

View full text Add to dashboard Cite

The scaling of a non-planar super-junction (SJ) Si MOSFET based on SOI technology for low voltage rating applications (below 50 V) requires a subsequent optimisation of SJ unit. The scaling and the SJ optimisation are carried out with physically based commercial TCAD device simulations by Silvaco. The study is based on a meticulous calibration of drift-diffusion simulations against experimental characteristics of a 1 µm gate length SJ multigate MOSFET (SJ-MGFET) aiming at improving density, switching speed, drive current, breakdown voltage (BV), and specific on-resistance (R on,sp). We investigate scaling of the device architecture to improve the device performance by optimizing doping profile to achieve an avalanche-enabled device under a charge balanced condition. The optimised SJ-MGFETs scaled by a factor of 0.5 and 0.25, with a folded alternating U-shaped n/p-SJ drift region pillar of a width of 0.3 µm and a trench depth of 2.7 µm, achieve a low specific on-resistance (R on,sp) of 7.68 mΩ.mm 2 and 2.24 mΩ. mm 2 (V GS = 10 V) and BV of 48 V and 26 V , respectively. The scaled 0.5 µm and 0.25 µm gate length SJ-MGFETs offer a transconductance (g m) of 20 mS/mm and 56 mS/mm at a drain voltage of 0.1 V , respectively, greatly improving the levels of integration in a CMOS architecture.

show abstract

Section: Device Structure Of the Sj-mgfetmentioning

confidence: 99%

Scaling and optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub–50 V applications

Adenekan

Holland

Kálna

2019

Microelectronics Reliability

View full text Add to dashboard Cite

show abstract

“…This transistor design follows closely the architecture of SJ-MGFETs reported in [6,7]. The whole transistor structure is grown on a buried oxide layer to mitigate the effect of substrateassisted depletion (SAD) [8,9,10]. The SJ-MGFET has a 1 µm gate length trenched in the channel of 0.5 µm length, creating a top surface (W top ) and a side wall (W side ) enclosure in the channel (non-planar technology).…”

Section: Device Structure Of Sj-mgfetmentioning

confidence: 99%

Optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub-100 V applications

Adenekan

Holland

Kálna

2018

Microelectronics Journal

View full text Add to dashboard Cite

The design and optimisation of a non-planar super-junction (SJ) Si MOS-FET based on SOI technology for low voltage rating applications (below 100 V) is carried out with physically based commercial 3-D TCAD device simulations using Silvaco. We calibrate drift-diffusion simulations to experimental characteristics of the SJ multi-gate MOSFET (SJ-MGFET) aiming at improving drive current, breakdown voltage (BV), and specific on-resistance (R on,sp). We investigate variations in the device architecture and improve device performance by optimizing doping profile under charge imbalance. The SJ-MGFET, using a folded alternating U-shaped n/p-SJ drift region pillar width of 0.3 µm with a trench depth of 2.7 µm achieves specific on-resistance (R on,sp) of 0.21 mΩ.cm 2 at a BV of 65 V. In comparison with conventional planar gate SJ-LDMOSFETs, the optimised SJ-MGFET gives 68% reduction in R on,sp and 41% increase in a saturation drain current at a drain voltage of 5 V and a gate voltage of 10 V.

show abstract

“…However, complex device structures are often introduced in these proposed technologies which make the industrial fabrication process very difficult and costly. Furthermore, even though device miniaturization is crucial for all voltage ranges, in the past few decades, most studies have been done on large LDMOS devices for mid-voltage and high-voltage applications [15][16][17][18][19][20][21][22][23][24][25][26][27]. And unfortunately, a thorough study on scaling of the planar LDMOS technology, limited to a straightforward planar device design, has not yet been performed.…”

Section: Introductionmentioning

confidence: 99%

Channel Length Optimization for Planar LDMOS Field-Effect Transistors for Low-Voltage Power Applications

Saadat

Put

Edwards

et al. 2020

IEEE J. Electron Devices Soc.

View full text Add to dashboard Cite

We identify an optimum channel length for planar Laterally Diffused Metal-Oxide-Semiconductor (LDMOS) field-effect transistors, in terms of the specific on-resistance, through systematic device simulation and optimization. We simulate LDMOS devices with different channel lengths ranging from 100 nm to 10 nm, modifying the length of the drift region and doping concentration of the body region to match a predetermined leakage current suitable for lowvoltage power applications (3.3V and 5V). For devices with a channel length exceeding 40 nm, reducing the channel length decreases the onresistance as expected. Below 40 nm, an increase in resistance is observed as the result of an increased body doping concentration leading to significant electron mobility degradation in the channel area.

show abstract

Novel Superjunction LDMOS (>950 V) With a Thin Layer SOI

Cited by 42 publications

References 15 publications

Scaling and optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub–50 V applications

Scaling and optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub–50 V applications

Optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub-100 V applications

Channel Length Optimization for Planar LDMOS Field-Effect Transistors for Low-Voltage Power Applications

Contact Info

Product

Resources

About

Novel Superjunction LDMOS (>950 V) With a Thin Layer SOI

Cited by 42 publications

References 15 publications

Scaling and optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub–50 V applications

Scaling and optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub–50 V applications

Optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub-100 V applications

Channel Length Optimization for Planar LDMOS Field-Effect Transistors for Low-Voltage Power Applications

Contact Info

Product

Resources

About

Scaling and optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub–50 V applications

Scaling and optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub–50 V applications

Optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub-100 V applications