Novel Through Silicon Vias Leakage Current Evaluation Using Infrared-Optical Beam Irradiation

Mizushima, Y.; Kitada, Hideki; Koshikawa, Kazushige; Suzuki, Shinsuke; Nakamura, Tomoji; Ohba, Takayuki

doi:10.7567/jjap.51.05ee03

Cited by 10 publications

(7 citation statements)

References 3 publications

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“…1). [3][4][5][6][7][8][9][10][11][12][13][14] Although ultrathin stacking is very attractive, it might cause degradation of device characteristics because of thinning-induced damage. However, in our previous studies, no such degradation was demonstrated for CMOS logic at 7 µm thickness and ferroelectric RAM at 9 µm thickness.…”

Section: Introductionmentioning

confidence: 99%

Impact of back-grinding-induced damage on Si wafer thinning for three-dimensional integration

Mizushima

Kim

Nakamura

et al. 2014

Jpn. J. Appl. Phys.

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Ultrathin wafers, which enable the low-aspect-ratio through-silicon vias to be formed easily, are indispensable for bumpless three-dimensional (3D) stacking. To clarify thinning-induced damage in detail, atomic-level defects occurring during wafer thinning and due to mechanical stress at microregions of the fracture surface have been studied. Such damage was evaluated by µ-Raman spectroscopy, laser microscopy, transmission electron microscopy, and positron annihilation spectroscopy. Coarse (#320 grit) grinding causes a roughly 500 MPa compressive stress, resulting in the formation of a less than 5 µm defect layer. Fine (#2000 grit) grinding enables the formation of a plane surface and reduces the stress to 100-200 MPa. However, a damaged layer of 200 nm still remains and an almost 100-nm-thick layer of vacancy-type defects exists. After chemical mechanical polishing (CMP), a stress-free surface was obtained and no defects were found except atomic-level vacancies, which were detected in a layer of 4 nm thickness after 1 µm CMP.

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Section: Introductionmentioning

confidence: 99%

Impact of back-grinding-induced damage on Si wafer thinning for three-dimensional integration

Mizushima

Kim

Nakamura

et al. 2014

Jpn. J. Appl. Phys.

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“…IR-OBIRCH analysis has been shown to be applicable for detecting abnormal insulation resistance by using the difference in the change in the electrical resistance induced by IR laser scanning between abnormal and normal areas. 21,22) In this analysis, the detected area was limited to around a dielectric surface because the IR laser that was used in the IR-OBIRCH analysis hardly penetrated the metal electrode in the MLCCs. Therefore, we needed to expose the dielectric near the degraded dielectric layer.…”

Section: Detection Of Degraded Area By Ir-obirch Analysismentioning

confidence: 99%

Analysis of insulation resistance degradation in Ni–BaTiO₃multilayer ceramic capacitors under highly accelerated life test

Sada

Fujikawa

2017

Jpn. J. Appl. Phys.

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The degradation mechanism of electrical breakdown in Ni–BaTiO3 multilayer ceramic capacitors (MLCCs) was studied by visualizing degraded areas in early failure and wear-out failure modes. The visualization was achieved by the fabrication of electrically degraded MLCCs just before electrical breakdown and by detection of the degraded area by infrared-optical-beam-induced resistance change (IR-OBIRCH) analysis. In the case of our prototype MLCCs, a thinner dielectric layer caused early failure and microstructural abnormalities in the dielectric layer caused wear-out failure. Such a visualization method directly demonstrates the causes of electrical breakdown in MLCCs.

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“…Stress at the center of the Cu plug decreases in proportion to the thickness of the Si wafer. The small aspect ratio provided by an ultrathin wafer also has the advantage of reducing stresses generated in the silicon itself, in the bottom and top Cu-TSV, and in interface regions having different CTEs [11,12,13].…”

Section: Wafer-level 3d Integration Processmentioning

confidence: 99%

Review of wafer-level three-dimensional integration (3DI) using bumpless interconnects for tera-scale generation

Ohba

Kim

Mizushima

et al. 2015

IEICE Electron. Express

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The prospects of three-dimensional (3D) integration for Terabyte large scale integration using bumpless interconnects with low-aspect-ratio TSVs and ultra-thinning are discussed. Bumpless (no bump) interconnects between wafers are a second-generation alternative to the use of microbumps for Wafer-on-Wafer (WOW) technology. Ultra-thinning of wafers down to 4 µm provides the advantage of a small form factor, not only in terms of the total volume of 3D ICs, but also the aspect ratio of ThroughSilicon-Vias (TSVs). Our bumpless interconnects technology is classified into Via-Last, which is performed from the front side after thinning, and stacking Back-to-Front, in which any number of thinned 300 mm wafers and/or heterogeneous dies can be integrated. From an economic point of view, in many situations WOW is the leading 3D process because stacking at the wafer level drastically increases the processing throughput, and using multi-level bumpless interconnects, with individual wiring die-to-die, provides an appropriate yield that is equivalent to or greater than that achievable with 2D processes when scaling down to 22 nm nodes and beyond.

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Novel Through Silicon Vias Leakage Current Evaluation Using Infrared-Optical Beam Irradiation

Cited by 10 publications

References 3 publications

Impact of back-grinding-induced damage on Si wafer thinning for three-dimensional integration

Impact of back-grinding-induced damage on Si wafer thinning for three-dimensional integration

Analysis of insulation resistance degradation in Ni–BaTiO₃multilayer ceramic capacitors under highly accelerated life test

Review of wafer-level three-dimensional integration (3DI) using bumpless interconnects for tera-scale generation

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Novel Through Silicon Vias Leakage Current Evaluation Using Infrared-Optical Beam Irradiation

Cited by 10 publications

References 3 publications

Impact of back-grinding-induced damage on Si wafer thinning for three-dimensional integration

Impact of back-grinding-induced damage on Si wafer thinning for three-dimensional integration

Analysis of insulation resistance degradation in Ni–BaTiO3multilayer ceramic capacitors under highly accelerated life test

Review of wafer-level three-dimensional integration (3DI) using bumpless interconnects for tera-scale generation

Contact Info

Product

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About

Analysis of insulation resistance degradation in Ni–BaTiO₃multilayer ceramic capacitors under highly accelerated life test