Novel TSV process technologies for 2.5D/3D packaging

Abstract

2.5D silicon interposers" and "Hetero 3D stacked" technology for high-performance LSI are gathering the most attention from now on. These technologies can solve interconnection problems using TSV (Through Silicon Via) to electrically connect stacked each function devises. 2.5D and hetero-3D Si integration has great advantages over conventional 2D devices such as high packaging density, small wire length, high-speed operation, low power consumption, and high feasibility for parallel processing. But, the radical problem about the long-term reliability of TSV production is not still solved. In particular, the management of barrier metal film deposition on the smooth surface is most important technology for Cu diffuse protection [1]. On the other hand, TSV isolation liner materials with high step coverage and lower temperature deposition on the smooth surface for high frequency devices will be necessary in the future. "Scallop-free" etching process has developed for TSV fabrication [2]. As a result, the smooth-sidewall had proved shorten PVD process time [3]. At first, it investigated a cost correlation of taper-shape etching and Cu-ECP (electrochemical plating) in this paper. And then, a polyurea film using a vapor deposition polymerization technology (which is Ulvac's FPF/PV large panel technology) tried introduction as isolation liner for next-generation high frequency device. And, it performed the film formation to a TSV pattern. IntroductionIn order to realize the manufacturing and cost benefits of via last technology for the 3D stacked integration, creation of TSV spanning all layers of fully formed chips must be realized. This is particularly new etching method challenging for TSV devices. The etcher system is using NLD (magnetic Neutral Loop Discharge) plasma that is a kind of high

Optimization of TSV Leakage in Via-Middle TSV Process for Wafer-Level Packaging

“…Through silicon via (TSV) technology has become attractive as a potential solution to further extend Moore's law through vertical connection to realize boosts in system performance and integration density while maintaining acceptable fabrication costs using wafer-level packaging [5]. Various studies have shown the process readiness of 2.5D Si interposer [6][7][8] or embedded TSV as wide I/O [9], although low-volume TSV technology is from via-last wafer-level packaging, which uses TSV with partial metal filling [10,11]. Although this is a more cost-effective wafer-level packaging solution, it is not suitable for implementation in applications such as sensors, RF, and power devices that require good signal quality, robust reliability, and acceptable fabrication costs under squeezed package sizes (both for planar format and vertical thickness).…”

Investigation into the manipulation of non-uniformity and undercut features of a positive profile through silicon via

“…A negative profile has a bottom width that is larger than its top width, and as a result a large part of the feature will be shadowed by the top opening of the profile. The straight profile has vertical 'cliff edges' which can cause difficulties obtaining a consistent film thickness and deposited material will naturally gravitate towards the bottom of the feature causing inconsistent film thicknesses [26]. One of the largest defects resulting from the positive etch process is the formation of a feature at the top of the profile that is often known as an 'overhang', 'undercut' or 'lateral etching'; where the area directly below the mask is narrower than the widest dimension of the TSV structure as shown in Figure 7b.…”

“…Figure 10: Effect of Mask Profile on Undercut [26] was drawn down the chamfer angle and continued until the line intersected the feature sidewall it corresponded with the bottom of the lateral etching region. To prove this effect researchers have deliberately created a chamfered feature at the mask hole edge and ran the same etch process on the sample.…”