Optimization of TSV Leakage in Via-Middle TSV Process for Wafer-Level Packaging

Liu, Xuanjie; Sun, Qizhen; Huang, Yiping; Chen, Zheng; Liu, Guoan; Zhang, David Wei

doi:10.3390/electronics10192370

Cited by 5 publications

(5 citation statements)

References 17 publications

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“…Some methods can also be adopted in the packaging substrate to facilitate fiber coupling, such as substrate hollowing out. For active silicon interposer, there are three main TSV fabrication processes, which are "TSV-first" [21], "TSV-middle" [22] and "TSV-last" [23], as shown in Figure 2.…”

Section: Structure Design Of 3d Optical Transceiver Modulementioning

confidence: 99%

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Design, Manufacture and Assembly of 3D Integrated Optical Transceiver Module Based on an Active Photonic Interposer

et al. 2022

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The new generation of data centers is further evolving towards the direction of high speed and intelligence, which puts forward a great demand for the iteration of optical interconnection technology. Three-dimensional integration based on active photonic interposers can achieve the advantages of high integration, high bandwidth and low power consumption, which has become the main direction for next generation optical module technology. The fabrication and assembly of 3D optical modules based on active interposer-integrated edge couplers and TSV are realized in this paper. Different active interposer processes with integrated edge couplers and RDL-TSV-RDL structures are discussed, manufactured, analyzed and evaluated. The problem of the co-fabrication of the TSV and edge coupler was solved, and perfect electrical and optical characteristics were also achieved. Finally, the fabrication of the substrate and the assembly of the 3D optical module were completed. This paper lays a solid foundation for the further research and large-scale application of 3D optical modules in the future.

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Section: Structure Design Of 3d Optical Transceiver Modulementioning

confidence: 99%

“…For active silicon interposer, there are three main TSV fabrication processes, which are "TSV-first" [21], "TSV-middle" [22] and "TSV-last" [23], as shown in Figure 2. In this paper, two dummy EIC (electrical integrated circuit) chips are designed for 3D assembly.…”

Section: Tiamentioning

confidence: 99%

Design, Manufacture and Assembly of 3D Integrated Optical Transceiver Module Based on an Active Photonic Interposer

et al. 2022

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“…As with rapid developments in consumer electronics and electric vehicles, silicon power devices play an increasingly crucial role [1]. Compared with silicon planar devices, which were the main application devices, trench structures enable a much smaller drain on resistance (Rdson) for the same chip area, significantly reducing overall conduction losses [2,3]. As the key stage in silicon power MOSFET manufacturing, trench etching processes directly influence the effect of subsequent processes as well as device performance.…”

Section: Introductionmentioning

confidence: 99%

Sidewall Modification Process for Trench Silicon Power Devices

et al. 2023

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In this study, trench sidewall modification processes were designed to improve profile uniformity and thereby enhance the electrical performance of silicon power devices in large-scale production. The effects of trench sidewall modification on the morphology, structure and electrical properties were studied. Plasma-induced damage in etching processes was also observed and briefly explained. Straight and smooth sidewall profiles were achieved through adjusting the SF6/CHF3 proportion in a combined etchant gas flow in the main etching procedure. By comparing HRSEM images from different etching protocols, it was evident that an enhanced CHF3 flow formed a proper passivation of the sidewall, eliminating the ion damages that are common in current main etch steps. To address the impurities introduced from the etchant gas and improve the gate oxide uniformity, further steps of depolymerization were applied in a plasma asher chamber, followed by wet clean steps. In the meantime, the plasma-induced charge accumulation effect was reduced by UV curing. Improved trench sidewall profiles and the gate oxide uniformity contributed to a lower leakage current between the gate and source terminals, leading to an overall yield enhancement of device properties in large-scale silicon wafer fabrication.

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“…Through-silicon-via (TSV) technology [1][2][3] is one of the most attractive threedimensional (3D) integration methods for high-speed and high-performance applications. It has the capability of electrically connecting and communicating densely-packed devices with different functionalities [3,4], such as integrated circuits and RF/microwave modules.…”

Section: Introductionmentioning

confidence: 99%

Electrical Characterization of Through-Silicon-via-Based Coaxial Line for High-Frequency 3D Integration (Invited Paper)

Zhao

Yuan

et al. 2022

Electronics

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Through-silicon-via (TSV)-based coaxial line techniques can reduce the high-frequency loss due to the low resistivity in the silicon substrate and thus can improve the efficiency of vertical signal transmission. Moreover, a TSV-based coaxial structure allows easily realizing the impedance matching in RF/microwave systems for excellent electrical performance. However, due to the limitations of existing available dielectric materials and the difficulties and challenges in the manufacturing process, ideal coaxial TSVs are not easy to obtain, and thus, the achieved electrical performance might be unexpected. In order to increase the flexibility of designing and manufacturing TSV-based coaxial structures and to better evaluate the fabricated devices, modeling and analysis theories of the corresponding high-frequency electrical performance are proposed in the paper. The theories are finally well validated using the finite-element simulation results, hereby providing guiding rules for selecting materials and improving manufacturing techniques in the practical process, so as to optimize the high-frequency performance of the TSV structures.

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Optimization of TSV Leakage in Via-Middle TSV Process for Wafer-Level Packaging

Cited by 5 publications

References 17 publications

Design, Manufacture and Assembly of 3D Integrated Optical Transceiver Module Based on an Active Photonic Interposer

Design, Manufacture and Assembly of 3D Integrated Optical Transceiver Module Based on an Active Photonic Interposer

Sidewall Modification Process for Trench Silicon Power Devices

Electrical Characterization of Through-Silicon-via-Based Coaxial Line for High-Frequency 3D Integration (Invited Paper)

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