Novel VLSI Algorithm and Architecture with Good Quantization Properties for a High-Throughput Area Efficient Systolic Array Implementation of DCT

Chiper, Doru Florin; Ungureanu, Paul

doi:10.1155/2011/639043

Cited by 20 publications

(5 citation statements)

References 31 publications

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“…In [32][33][34][35][36][37][38][39], we see a hardware accelerator for the computation of DCT-IV. In the proposed method, each data from the input sequence is fed to a multiplier and to an accumulator.…”

Section: Comparisonmentioning

confidence: 99%

A New Approach for a Unified Architecture for Type IV DCT/DST with an Efficient Incorporation of Obfuscation Technique

Chiper

Cotorobai

2021

Electronics

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This paper aims at solving one challenging problem in designing VLSI chips, namely, the security of the hardware, by presenting a new design approach that incorporates the obfuscation technique in the VLSI implementation of some important DSP algorithms. The proposed method introduces a new approach in obtaining a unified VLSI architecture for computing type IV discrete cosine transform (DCT-IV) and type IV discrete sine transform (DST-IV), with an efficient integration of the obfuscation technique, while maintaining low overheads. The algorithms for these two transforms were restructured in such a way that their structures are fairly similar, and thus they can be implemented on the same VLSI chip and on the same hardware with very few modifications, with the latter being attributed to the pre-processing and post-processing stages. The design proposed uses the regular and modular structures, which are named quasi-correlation, and the architecture is inspired by the paradigm of the systolic array architecture. Thus, the introduced design benefits the security, for the hardware, and also the advantages introduced by the use of the regular and modular structures. A very efficient, unified VLSI architecture for type IV DCT/DST can be obtained, which allows the computation of the two algorithms on the same hardware, allowing an efficient incorporation of the obfuscation technique with very low overheads, and it can be very efficiently implemented, offering high-speed performances and low hardware complexity, with the latter being attributed to the efficient use of the hardware resources for the computation of these two algorithms.

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Section: Comparisonmentioning

confidence: 99%

A New Approach for a Unified Architecture for Type IV DCT/DST with an Efficient Incorporation of Obfuscation Technique

Chiper

Cotorobai

2021

Electronics

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“…It is highly parallel using a low hardware complexity structure. The multipliers with a constant in MUL blocks can be efficiently implemented in hardware using the techniques proposed in [20]- [24]. Parallel processing is one of the major ways to reduce power consumption, the high processing speed being traded off for low power using the reduction of the supply voltage value [26].…”

Section: Highly Parallel Vlsi Architecturementioning

confidence: 99%

Novel DHT Algorithm Implementation Using Sharing Multipliers

Venkatesh¹,

Sudhakar²

2014

IJAREEIE

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ABSTRACT:A new very large scale integration (VLSI) algorithm for a 2 -length discrete Hartley transform (DHT) that can be efficiently implemented on a highly modular and parallel VLSI architecture having a regular structure is presented. In the proposed method multiply the multipliers by using array multiplier and to add the co-efficients by using Carry Look-ahead Adder (CLA). In the proposed system we are reducing the area by using the array multiplier and Carry Look-ahead Adder (CLA). The DHT algorithm can be efficiently split on several parallel parts that can be executed concurrently. Moreover, the proposed algorithm is well suited for the sub expression sharing techniques that can be used to significantly reduce the hardware complexity of the highly parallel VLSI implementation. Using the advantages of the proposed algorithm and the fact that we can efficiently share the multipliers with the same constant, the number of the multipliers has been significantly reduced such that the number of multipliers is very small comparing with that of the existing algorithms. Moreover, the multipliers with a constant can be efficiently implemented in VLSI. KEYWORDS:Discrete Hartley transform (DHT), DHT domain processing, fast algorithms. I. INTRODUCTIONThe Discrete Fourier transform (DFT) is used in many digital signal processing applications as in signal and image compression techniques, filter banks [1], signal representation, or harmonic analysis [2]. The discrete Hartley transform (DHT) [2], [3] can be used to efficiently replace the DFT when the input sequence is real. In the literature, there are some fast algorithms for the computation of and some algorithms for the computation of generalized DHT [8]- [10]. There are also several split-radix algorithms for computing DHT with a low arithmetic cost. Thus, Sorensen et al. [11] and Malvar [12] proposed split-radix algorithms for DHT with a low arithmetic cost. Bi [13] proposed another split-radix algorithm where the odd-indexed transform outputs are computed using an indirect method. The classical split-radix algorithm is difficult to implement on VLSI due to its irregular computational structure and due to the fact that the butterflies significantly differ from stage to stage. Thus, it is necessary to derive new such algorithms that are suited for a parallel VLSI system. There are also in the literature several fast algorithms that use a recursive strategy as those in [14] for discrete cosine transform (DCT) and that in [10] for generalized DHT. Since DHT is computationally intensive, it is necessary to derive dedicated hardware implementations using the VLSI technology. One category of VLSI implementations is represented by systolic arrays. There are many systolic array implementations of . Systolic array architectures are modular and regular, but they use particularly pipelining and not parallel processing to obtain a highspeed processing. In the literature, highly parallel solutions as those in [8] and [19] were also proposed. In [8], a highly parallel and modu...

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“…The performances of a VLSI algorithm are determined even more by the communication complexity and structure and then by its arithmetic complexity. Hence, using regular and modular computational structures can lead to good hardware implementation solutions for the discrete transforms [2][3][4][5][6][7] using systolic arrays [8] or distributed arithmetic [9]. As can be seen, this approach offers reduced hardware complexity with low I/O cost and high speed with good topological features.…”

Section: Introductionmentioning

confidence: 99%

An Efficient Algorithm and Architecture for the VLSI Implementation of Integer DCT That Allows an Efficient Incorporation of the Hardware Security with a Low Overhead

Chiper

Cracan

2023

Applied Sciences

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In this paper, we propose a new hardware algorithm for an integer based discrete cosine transform (IntDCT) that was designed to allow an efficient VLSI implementation of the discrete cosine transform using the systolic array architectural paradigm. The proposed algorithm demonstrates multiple benefits specific to integer transforms with efficient hardware implementation and sufficient precision in approximating irrational transform coefficients for practical applications. The proposed integer DCT algorithm can be efficiently restructured into five regular and modular computational structures of lengths of four and one of length two called pseudo-cycle convolutions which translate into efficient VLSI implementations using systolic arrays. Moreover, besides an efficient VLSI implementation with high-speed performances due to the parallel decomposition of the proposed integer DCT algorithm, the proposed VLSI architecture uses a tag control mechanism that facilitates the integration of an obfuscation technique that significantly improves the hardware security with low overheads, maintaining all the implementation performances.

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Novel VLSI Algorithm and Architecture with Good Quantization Properties for a High-Throughput Area Efficient Systolic Array Implementation of DCT

Cited by 20 publications

References 31 publications

A New Approach for a Unified Architecture for Type IV DCT/DST with an Efficient Incorporation of Obfuscation Technique

A New Approach for a Unified Architecture for Type IV DCT/DST with an Efficient Incorporation of Obfuscation Technique

Novel DHT Algorithm Implementation Using Sharing Multipliers

An Efficient Algorithm and Architecture for the VLSI Implementation of Integer DCT That Allows an Efficient Incorporation of the Hardware Security with a Low Overhead

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