Novell embedded microbump approach for die-to-die and wafer-to-wafer interconnects with variable microbump diameters and down to 5 um interconnect pitch scaling

Derakhshandeh, Jaber; Heyvaert, C.; Beirnaert, F.; Cochet, Tom; Bex, Pieter; Hou, Lin; Lofrano, Melina; Jamieson, Geraldine; Heylen, N.; Suhard, Samuel; Honoré, M.; Beyne, Eric; Webers, Tomas; Bertheau, J.; Phommahaxay, Alain; Plas, G. Van der; Rebibis, Kenneth June; Miller, Andy; Beyer, Gerald; Capuz, Giovanni; Inoue, Fumihiro; Cherman, Vladimir; Preter, Inge De; Duval, Fabrice; Slabbekoorn, John; Gerets, Carine

doi:10.23919/empc44848.2019.8951856

Cited by 3 publications

(4 citation statements)

References 3 publications

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“…EMICONDUCTOR technology for high performance applications requires high I/O number, which can be realized by tiny interconnects provided by microbumps or Cu pads at very small pitch. Conventional microbumps with solder are limited to a minimum of 10 µm pitch because of bump bridging or solder shorts (squeeze out of solder from the bonding area) [1][2][3][4]. Pitch reduction requires tough alignment accuracy and tilt control which are especially challenging for controlled solder collapse and for thermo-compression bonding (TCB).…”

Section: Introductionmentioning

confidence: 99%

“…Pitch reduction requires tough alignment accuracy and tilt control which are especially challenging for controlled solder collapse and for thermo-compression bonding (TCB). Small solder volumes are consumed rather fast during bonding and therefore pose a challenge for the joint formation [3,4] on top of the manufacturing challenges. Recently, the technologies based on embedding of microbumps in a polymer were published [2,4].…”

Section: Introductionmentioning

confidence: 99%

“…Small solder volumes are consumed rather fast during bonding and therefore pose a challenge for the joint formation [3,4] on top of the manufacturing challenges. Recently, the technologies based on embedding of microbumps in a polymer were published [2,4]. However, hybrid bonding appears to be a more promising technology for 3D stacking in terms of increasing the interconnect density and scaling the interconnect size.…”

Section: Introductionmentioning

confidence: 99%

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Microstructure Development of Cu/SiO₂ Hybrid Bond Interconnects After Reliability Tests

Panchenko

Wambera

Mueller

et al. 2022

IEEE Trans. Compon., Packag. Manufact. Technol.

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The focus of this study is a detailed characterization of hybrid Cu/SiO2 wafer-to-wafer bonding interconnects after reliability testing. Hybrid bonding (or direct bond interconnect) is a technology of choice for fine pitch bonding without microbumps. The main challenge of the hybrid bonding technology is the preparation of a clean Cu/SiO2 surface with controlled Cu dishing. The Cu/Cu interface after hybrid bonding and after reliability testing was investigated by electron backscatter diffraction (EBSD) in this study. The Cu interconnects (diameter 4 μm and pitch 18 μm) enclosed by SiO2 were formed by wafer-to-wafer bonding. The small diced stacks were used for subsequent reliability tests. Three types of tests were carried out: temperature shock test (TST) at -40 °C / 125 °C up to 1000 cycles, isothermal storage at 150 °C, 300 °C, and 400 °C as well as multiple bonding cycles. The results include a comprehensive estimation of the changes in grain diameter, grain boundaries and texture of the interconnects. All samples showed good reliability and stayed intact after all tests. Grain refinement was observed after TST, storage at 150 °C, and multiple bonding cycles compared to the state after bonding. Grain growth was found for the storage at 300/400 °C (up to 6 h). No significant changes in texture were found after the reliability tests. The <111> direction with its characteristic <115> twin orientation are the dominating orientations perpendicular to the bonding interface. The migration of 60 ° twin boundaries has been observed after reliability testing. The results indicate a rotation towards nearby high angle grain boundaries (60 to 45 °).

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Microstructure Development of Cu/SiO₂ Hybrid Bond Interconnects After Reliability Tests

Panchenko

Wambera

Mueller

et al. 2022

IEEE Trans. Compon., Packag. Manufact. Technol.

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“…In order to overcome the observed problems with microbump sliding and interlocking during TCB, we introduced the use of metal-damascene pads. 7,8) Instead of building structures on the die surface, a metal pad is formed in the chip passivation layer (see Fig. 1), resulting in no topography on the bottom wafer at the bonding interface.…”

Section: Introductionmentioning

confidence: 99%

Fine-pitch bonding technology with surface-planarized solder micro-bump/polymer hybrid for 3D integration

Inoue¹,

Derakhshandeh²,

Lofrano³

et al. 2021

Jpn. J. Appl. Phys.

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The scaling of conventional solder-based flip chip bonding is facing its limitations due to thermal compression bonding overlay tolerance when using conventional bumping. To decrease the tolerance, planarization can be used to fabricate two flat surfaces for bonding. However, planarization of these soft and ductile surfaces is challenging by polishing. Here, we assess the creep-feed fly-cutting process, the so-called surface planer process for planarization of fine-pitch Sn bumps and polymer simultaneously. It is revealed that the polishing process causes a lot of scratches on the Sn and polymer surface; however, these surfaces are smooth for the case of the surface planer process. The planarized Sn and polymer surface has only a 50 nm step height which does not have any impact during thermal compression bonding. Using a planarized Sn and polymer surface, stacking of below 10 μm pitch has been achieved.

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Comparison of Diffusion Barrier Properties of Ni–Fe and Ni–Fe–W Layer at the Cu/Sn Interface

Liu,

Li,

Liu

et al. 2024

Electron. Mater. Lett.

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Novell embedded microbump approach for die-to-die and wafer-to-wafer interconnects with variable microbump diameters and down to 5 um interconnect pitch scaling

Cited by 3 publications

References 3 publications

Microstructure Development of Cu/SiO₂ Hybrid Bond Interconnects After Reliability Tests

Microstructure Development of Cu/SiO₂ Hybrid Bond Interconnects After Reliability Tests

Fine-pitch bonding technology with surface-planarized solder micro-bump/polymer hybrid for 3D integration

Comparison of Diffusion Barrier Properties of Ni–Fe and Ni–Fe–W Layer at the Cu/Sn Interface

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