Noxim: An open, extensible and cycle-accurate network on chip simulator

Catania, Vincenzo; Mineo, Andrea; Monteleone, Salvatore; Palesi, Maurizio; Patti, Davide

doi:10.1109/asap.2015.7245728

Cited by 223 publications

(84 citation statements)

References 7 publications

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“…The traces have been extracted from the GEM5 full-system simulator [41]. To simulate a 3D CMP architecture, the extracted traces from GEM5 are interfaced with 3D Noxim, as a 3D NoC simulator [42]. Figure 1 shows the eCMP at 32-nm technology for use in our experiment, which contains 64 cores on a core layer and 64 memory banks on the memory layer.…”

Section: Platform Setupmentioning

confidence: 99%

Low-power heterogeneous uncore architecture for future 3D chip-multiprocessors

et al. 2018

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Uncore components such as on‐chip memory systems and on‐chip interconnects consume a large amount of energy in emerging embedded applications. Few studies have focused on next‐generation analytical models for future chip‐multiprocessors (CMPs) that simultaneously consider the impacts of the power consumption of core and uncore components. In this paper, we propose a convex‐optimization approach to design heterogeneous uncore architectures for embedded CMPs. Our convex approach optimizes the number and placement of memory banks with different technologies on the memory layer. In parallel with hybrid memory architecting, optimizing the number and placement of through silicon vias as a viable solution in building three‐dimensional (3D) CMPs is another important target of the proposed approach. Experimental results show that the proposed method outperforms 3D CMP designs with hybrid and traditional memory architectures in terms of both energy delay products (EDPs) and performance parameters. The proposed method improves the EDPs by an average of about 43% compared with SRAM design. In addition, it improves the throughput by about 7% compared with dynamic RAM (DRAM) design.

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Section: Platform Setupmentioning

confidence: 99%

Low-power heterogeneous uncore architecture for future 3D chip-multiprocessors

et al. 2018

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“…The traces have been extracted from the GEM5 full-system simulator [17]. For simulating a 3D CMP architecture, the extracted traces from GEM5 were interfaced with 3D Noxim, as a 3D NoC simulator [49]. GEM5 was augmented with McPAT and 3D Noxim with ORION [50] to calculate the power consumption in this paper.…”

Section: Platform Setupmentioning

confidence: 99%

A novel power model for future heterogeneous 3D chip-multiprocessors in the dark silicon age

2018

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Dark silicon has recently emerged as a new problem in VLSI technology. Maximizing performance of chip-multiprocessors (CMPs) under power and thermal constraints is very challenging in the dark silicon era. Providing next-generation analytical models for future CMPs which consider the impact of power consumption of core and uncore components such as cache hierarchy and on-chip interconnect that consume significant portion of the on-chip power consumption is largely unexplored. In this article, we propose a detailed power model which is useful for future CMP power modeling. In the proposed architecture for future CMPs, we exploit emerging technologies such as non-volatile memories (NVMs) and 3D techniques to combat dark silicon. Results extracted from the simulations are compared with those obtained from the analytical model. Comparisons show that the proposed model accurately estimates the power consumption of CMPs running both multi-threaded and multi-programed workloads.

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“…Noxim was developed by Palesi et al, and implemented in SystemC [3]. Noxim provides a variety of options to simulate 2-D NoC.…”

Section: A Noximmentioning

confidence: 99%

“…Noxim [3] and NoCTweak [4] are notable examples. Most of the NoC simulators focus on evaluating metrics, like throughput and energy dissipation on the NoC platform level.…”

Section: Introductionmentioning

confidence: 99%

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Clustered Networks-on-Chip: Simulation and Performance Evaluation

Hassan¹

2017

IJCDS

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In many-core Networks-on-Chip (NoC) systems, two topics have recently been researched; NoC clustering and NoC simulation. NoC clustering investigates grouping processing elements (PEs) based on common characteristics between them, like spatial locality or communication patterns. Research showed that NoC clustering achieved better performance and load balancing. Furthermore, it allows scalability of the NoC grid. The other topic, NoC simulation, provides tools for early evaluation of NoC systems. This allowed easy investigation of NoC systems with large number of PEs. Plenty of research has been done in both topics separately. In this paper, we try to fill the gap. We extend an existing NoC simulation tool by adding support for simulating NoC clusters and inter-NoC traffic. The presented NoC clustering simulator supports the modular design technique, which in turn offers the flexibility in configuring cluster parameters. Examples of configurable parameters that are supported by our modified simulator are: adding interconnection topologies to configure how the NoC entities are connected with each other, adding a cluster manager that maps tasks to NoC entities based on the inter-NoC communication pattern, adding latency factors of cluster links in the case of inter-NoC traffic, and adapting the routing algorithm for both inter-cluster and intra-cluster traffic. A clustered NoC simulation case study shows the effectiveness of the modifications made to the simulator. For example, a certain NoC setup is simulated twice, initially non-clustered then clustered, using the added features. Collected data shows that the average clustered NoC routers' energy consumption is 50% lower than the consumption in the non-clustered case.

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Noxim: An open, extensible and cycle-accurate network on chip simulator

Cited by 223 publications

References 7 publications

Low-power heterogeneous uncore architecture for future 3D chip-multiprocessors

Low-power heterogeneous uncore architecture for future 3D chip-multiprocessors

A novel power model for future heterogeneous 3D chip-multiprocessors in the dark silicon age

Clustered Networks-on-Chip: Simulation and Performance Evaluation

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