Numerical analysis on the effects of different inlet gates and gap heights in TQFP encapsulation process

Effect of stacking chips and inlet positions on void formation in the encapsulation of 3D stacked flip-chip package

“…The viscosity behavior of the EMC is described by the CastroMacosko model [3,4,17,19] to predict the relationship between the viscosity and degree of polymerization given by…”

“…The curing kinetics of the EMC was described using Kamal's equation [3,4,17,19], which is integrated with the Castro-Macosko model in the current study. In this model, the rate of chemical conversion of the compound can be predicted as follows:…”

“…However, the occurrence of void formation reduces package reliability during the encapsulation process. This problem was mentioned in various IC encapsulation processes, such as the thin quad flat package (TQFP) [3,4], TSOP II 54L LOC [5,6], stacked-chip scale package (S-CSP) [7][8][9][10], mold array package (MAP) [11], and molded underfill [12].…”

“…They also reported that the void size decreases with the increasing inlet flow rate. Khor et al [4] used the finite volume method (FVM) to study the extension of the TQFP encapsulation and the FLUENT software to perform the simulation analysis. The utilization of the multi-gate inlet and the change in gap height in the TQFP design promise the reduction of filling time and minimization of the chances of void formation.…”

“…Modeling tools, such as PLICE-CAD [2], FORTRAN [7][8][9], FLUENT [4,10], C-MOLD [6,14], and Moldex3D [15], have been used for the continuous improvement of various types of IC packages. The commercial computer-aided engineering (CAE) and the finite elementbased software assist researchers in enhancing the deformation of wire bonding [16] and paddle shift [17,18] during the encapsulation process.…”