Numerical and experimental investigations of large IC flip chip attach

Schubert, Andreas; Dudek, R.; Leutenbauer, R.; Coskina, P.; Becker, K.-F.; Kloeser, J.; Michel, B.; Reichl, H.; Baldwin, D.F.; Qu, Jianmin; Sitaraman, Suresh K.; Wong, Ching‐Ping; Tummala, Rao

doi:10.1109/ectc.2000.853353

Cited by 12 publications

(6 citation statements)

References 8 publications

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“…The underfill, filling the gap between the chip and substrate, reduces the thermo-mechanical stresses of solder joints. With the underfill, the chip deformation under external loading can still be measured [25], and the chip lateral motion is dampened, some of which is converted to the vertical motion [26], facilitating the modal shape reconstruction based on the vertical vibration responses. The thermal pad attached to the chip surface is applied to enhance the heat dissipation of the chip [27].…”

Section: Resultsmentioning

confidence: 99%

Defect detection of flip-chip solder joints using modal analysis

Liu¹,

Shi²,

Wang³

et al. 2012

Microelectronics Reliability

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Section: Resultsmentioning

confidence: 99%

Defect detection of flip-chip solder joints using modal analysis

Liu¹,

Shi²,

Wang³

et al. 2012

Microelectronics Reliability

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“…Also the coefficients of thermal expansion (CTE) are nearly the same (CTE Pyrex = 3 ppm/K; CTE Si = 4 ppm/K). A visual comparison with results from scanning acoustic microscopy on silicon dice ( [1], [2]) showed a similar appearance of delaminations. The used experimental setup was able to analyze different sample configurations with low effort.…”

Section: Optical Methodsmentioning

confidence: 57%

“…It starts locally at the UBM and grows with an ellipse-like shape. The higher peel stress in the bump vicinity seems to be the reason for that behavior ( [2]). Finally it unites with neighboring delaminations.…”

Section: Resultsmentioning

confidence: 93%

“…As illustrated in figures 8, 9 delamination starts earlier and N c33 is reached later with the larger chips. Investigations in [2] computed a higher creep strain range for load bumps in a zone at the chip edge. The size of this zone was nearly the same for different die sizes.…”

Section: Effect Of Chip Sizementioning

confidence: 98%

“…(e.g. [1], [2]) This technique is expensive, time-consuming and offers only limited resolution. In this paper, a novel accurate methodology is presented.…”

Section: Introductionmentioning

confidence: 99%

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Mechanism and growth rate of underfill delaminations in flip chips

Jakschik¹,

Feustel

Meusel

2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)

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Delamination of underfill in flip chips is a widely accepted major cause for failure. However, there is a lack of information on the mechanism of this effect. A novel methodology is used to examine these delaminations in this paper. Instead of the expensive and time-consuming scanning acoustic microscopy with limited resolution, an optical method is established. For that the silicon chip was replaced by a glass chip (Pyrex). With usual passivations, the component is comparable to silicon flip chips from the mechanical point of view.This gives the possibility to look at the interface underfill/passivation or underfill/PCB by a microscope and a CCD camera. Photo analysis software allows to quantify delaminated versus not delaminated regions. Hence, an evaluational method for material and geometric impacts to delaminations is available.The effect of the following parameters were observed. -chip size, bump height, substrate thickness -passivation, underfill material -flux material, die sites with and without solder resist Beside other results, it has been shown, that the most reliable combination was made of 0.8mm substrate, a passivation of SiO 2 and no use of solder resist. A good meniscus could improve the hydro-thermal fatigue. As a function of geometric parameters different behavior of crack growth were found. IntroductionA well-founded life time prediction for flip chip components requires a well-proved knowledge about the principle of possible failure. One major risk are delaminations of underfill. They may occur at the interface underfill/passivation, underfill/bump or underfill/printed circuit board. (fig.:1) However, there is a lack of information on this effect.The experimental observation of delamination is typically done by scanning acoustic microscopy. (e.g.[1], [2]) This technique is expensive, time-consuming and offers only limited resolution. In this paper, a novel accurate methodology is presented. In a second part the influence of geometry and process parameters regarding their impact on delamination initiation and crack growth are discussed.

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