Numerical investigation of excess RF channel noise in sub-100 nm MOSFETs

Mahajan, Vinayak; Jindal, R.P.; Shichijo, H.; Martin, Samuel P.; Hou, Fan-Chi; Trombley, Django

doi:10.1109/edst.2009.5166104

Cited by 8 publications

(4 citation statements)

References 18 publications

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“…Some authors [30] attribute part of this excess noise to the noise contribution due to a shot noise associated with a diffusion current at the source side of the channel. However, device simulations using drift-diffusion and hydrodynamic models for sub-100 nm MOSFETs report noise less than the noise seen experimentally [31]. Additional noise mechanisms or noise contributions must be taken into account in simulations in order to explain the experimental results.…”

Section: Resultsmentioning

confidence: 99%

“…Figures 3(b) and 7(b) show an important increase in the drain excess noise ratio γ when heating is considered. Also, important However, experimental results from different authors [28][29][30][31][32][33] for SG MOSFETs for various lengths found excess noise ratios γ greater than 1 for short-channel devices below 100 nm. Also experimental results [29,30] show an important increase of γ with drain voltage for sub-100 nm gate lengths SG MOSFET devices.…”

Section: Resultsmentioning

confidence: 99%

“…Substituting the expression of dV ( 21) in (31), the following compact expression for the drain noise spectral density is obtained:…”

Section: Compact Noise Expressionsmentioning

confidence: 99%

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High-frequency compact analytical noise model of gate-all-around MOSFETs

Lázaro¹,

Nae²,

Muthupandian³

et al. 2010

Semicond. Sci. Technol.

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Silicon-on-insulator (SOI) MOSFETs are excellent candidates for replacing the current conventional bulk technologies. The most promising SOI devices are based on multiple gate structures, among these the surrounding gate (SGT) MOSFET being one of the best candidates for the downscaling of complementary CMOS technology toward the sub-50 nanometer channel length range. In these devices, the transition frequency f t is greatly increased, making them suitable for high-frequency applications. This makes the RF and microwave modeling, as well as high-frequency noise studies of these devices, a matter of utmost importance. In this paper, we present compact expressions to model the drain and gate current noise spectrum densities and their correlation for SGT MOSFETs. Using this model, the SGT MOSFET noise performances are studied. The current and noise models, due to their explicit analytical expressions, can be easily introduced in circuit simulators.

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

See 1 more Smart Citation

High-frequency compact analytical noise model of gate-all-around MOSFETs

Lázaro¹,

Nae²,

Muthupandian³

et al. 2010

Semicond. Sci. Technol.

View full text Add to dashboard Cite

show abstract

“…For nanoscale devices with feature sizes below 100 nm, it is still debated whether short-channel effects, as discussed above, are adequate for describing the effects of shortchannel noise [44]. Some researchers have suggested that shot noise is better able to describe the noisy behavior for FETs below 40 nm [34,45,46].…”

Section: Results and Comparisons Of Modeling Noise In Short-mentioning

confidence: 99%

The Design of Low Noise Amplifiers in Deep Submicron CMOS Processes: A Convex Optimization Approach

Hoe

Jin

2015

VLSI Design

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With continued process scaling, CMOS has become a viable technology for the design of high-performance low noise amplifiers (LNAs) in the radio frequency (RF) regime. This paper describes the design of RF LNAs using a geometric programming (GP) optimization method. An important challenge for RF LNAs designed at nanometer scale geometries is the excess thermal noise observed in the MOSFETs. An extensive survey of analytical models and experimental results reported in the literature is carried out to quantify the issue of excessive thermal noise for short-channel MOSFETs. Short channel effects such as channel-length modulation and velocity saturation effects are also accounted for in our optimization process. The GP approach is able to efficiently calculate the globally optimum solution. The approximations required to setup the equations and constraints to allow convex optimization are detailed. The method is applied to the design of inductive source degenerated common source amplifiers at the 90 nm and 180 nm technology nodes. The optimization results are validated through comparison with numerical simulations using Agilent’s Advanced Design Systems (ADS) software.

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Physics of Noise Performance of Nanoscale Bulk MOS Transistors

Jindal

2010

Compact Modeling

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Numerical investigation of excess RF channel noise in sub-100 nm MOSFETs

Cited by 8 publications

References 18 publications

High-frequency compact analytical noise model of gate-all-around MOSFETs

High-frequency compact analytical noise model of gate-all-around MOSFETs

The Design of Low Noise Amplifiers in Deep Submicron CMOS Processes: A Convex Optimization Approach

Physics of Noise Performance of Nanoscale Bulk MOS Transistors

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