Numerical Simulation of Bottom Oxide Thickness Effect on Charge Retention in SONOS Flash Memory Cells

Abstract

In this paper, bottom-oxide thickness (T bo ) and program/erase stress effects on charge retention in SONOS Flash memory cells with FN programming are investigated. Utilizing a numerical analysis based on a multiple electron-trapping model to solve the Shockley-Read-Hall rate equations in nitride, we simulate the electron-retention behavior in a SONOS cell with T bo from 1.8 to 5.0 nm. In our model, the nitride traps have a continuous energy distribution. A series of Frenkel-Poole (FP) excitation of trapped electrons to the conduction band and electron recapture into nitride traps feature the transitions between the conduction band and trap states. Conduction band electron tunneling via oxide traps created by high-voltage stress and trapped electron direct tunneling through the bottom oxide are included to describe various charge leakage paths. We measure the nitride-charge leakage current directly in a large-area device for comparison. This paper reveals that the charge-retention loss in a high-voltage stressed cell, with a thicker bottom oxide (5 nm), exhibits two stages. The charge-leakage current is limited by oxide trap-assisted tunneling in the first stage and, then, follows a 1/t time dependence due to the FP emission in the second stage. The transition time from the first stage to the second stage is related to oxide trap-assisted tunneling time but is prolonged by a factor. Index Terms-Oxide thickness, positive oxide charge-assisted tunneling, Shockley-Read-Hall (SRH) rate equation, SONOS retention mechanisms.

Impact of the charge transport in the conduction band on the retention of Si-nitride based memories

“…This improved model allows us to simulate the programming and retention sequence; therefore, differently from [3]- [5], [7] no assumption is needed on the spatial distribution of the trapped charge at the beginning of the retention phase.…”

Charge Retention Loss in a $\hbox{HfO}_{2}$ Dot Flash Memory via Thermally Assisted Tunneling

“…The direction of the gate current flow indicates the escape of programmed electrons through a top oxide in the HfO 2 cell. Second, the gate current in both SONOS [6] and HfO 2 dot flash cells exhibits 1/t time dependence. The 1/t characteristic can be derived either from a tunneling front model [7] or from a Frenkel-Poole (FP) emission model [8].…”

Dependence of Electrons Loss Behavior on the Nitride Thickness and Temperature for Charge Trap Flash Memory Applications

“…Recently, CTF memory devices have gained increasing interest in the three dimensional (3D) integration for next generation nonvolatile memory technology [4,5]. The tunnel oxide thickness plays a crucial role in regulating the erasing speed, data retention characteristics and charge loss mechanisms for CTF memory devices [6], while the thickness of the nitride charge trapping layer is less critical. Nevertheless, in 3D architectures, the nitride thickness has a direct effect on charge storage performance and array density [7].…”