This letter solves a major hurdle that mars photolithography-based fabrication of micro-mesoscale structures in silicon. Conventional photolithography is usually performed on smooth, flat wafer surfaces to lay a 2D design and subsequently etch it to create single-level features. It is, however, unable to process non-flat surfaces (already etched wafers) to create more than one level to give rise to multi-level, 3D, hierarchical structures in the substrate. In this study, we have described a novel cleanroom-based process flow that allows for easy creation of such multi-level, hierarchical structures in a substrate. This is achieved by introducing an ultra-thin sacrificial silicon dioxide hardmask layer on the substrate, which is first 3D patterned via multiple rounds of lithography. Then, this 3D pattern is scaled vertically by a factor of 200 – 300 and transferred to the substrate underneath via a single shot deep etching step. The proposed method is also easily characterizable. Using features of different topographies and dimensions, the etch rates and selectivities were quantified, these characterization information were later used while fabricating specific target structure. Furthermore, this study comprehensively compares the novel pattern transfer technique to already existing methods of creating multi-level structures, like grayscale lithography, chip stacking and double-sided etching. The proposed process was found to be cheaper, faster, and easier to standardize compared to other methods – this makes the overall process more reliable and repeatable. We hope it will encourage more research into hybrid structures that hold the key to dramatic performance improvements in several micro-mesoscale devices.