Numerical Simulation of Static Noise Margin for a Six-Transistor Static Random Access Memory Cell with 32nm Fin-Typed Field Effect Transistors

Abstract

Abstract. We in this paper for the first time explore the static noise margin (SNM) of a six-transistor (6T) static random access memory (SRAM) cell with nanoscale silicon-on-insulator (SOI) fin-typed field effect transistors (FinFETs). The SNM is calculated with respect to the supply voltage, operating temperature, and cell ratio by performing a three-dimensional mixed-mode simulation. To include the quantum mechanical effect, the density-gradient equation is simultaneously solved in the coupled device and circuit equations. The standard deviation (σSNM ) of SNM versus device's channel length is computed, based upon the design of experiment and response surface methodology. Compared with the result of SNM for SRAM with 32nm planar metal-oxide-semiconductor field effect transistors, SRAM with SOI FinFETs quantitatively exhibits higher SNM and lower σSNM . Improvement of characteristics resulting from good channel controllability implies that SRAM cells fabricated with FinFETs continuously maintains cell stability in sub-32nm technology nodes.

Impact of lanthanum doped zirconium oxide (LaZrO2) gate dielectric material on FinFET inverter

“…The NM of the simulated circuit is improved by 17% (0.375 V) as compared to results derived by authors for nanowire field-effect transistorbased inverter (0.32 V) (Nayak et al, 2014). The determined static power consumption for a circuit is 3×10 −14 W (Li et al, 2007). The dependence of noise margin on temperature (273, 300, 398 K) and voltage (0.4, 0.8, 1.2 V) variations have been analyzed for LaZrO 2 gate dielectric and delineated in Table 5.…”

“…This material is chemically stable in contact with Silicon and has high crystallization temperature, high dielectric constant and wide energy band gaps (~6 eV) as compared to SiO 2 . It has deposited on an active silicon channel by atomic layer deposition (ALD) and chemical vapor deposition (CVD) method at high temperature (Gaskell et al, 2007;Zhao et al, 2012;Liu et al, 2019;Chen et al, 2004). The on-current showed the progress of 2.7 × and off-current demonstrated diminishing by 10 −1 in high-k gate dielectric compared to conventional SiO 2 .…”

“…The butterfly curve (VTC) of the FinFET-based inverter has delineated in Figure 9 for et al, 2014). The determined static power consumption for a circuit is 3×10 −14 W (Li et al, 2007).…”

“…In sub-22 nm technology, the direct tunneling gate leakage current has reduced with novel high-k gate dielectric materials like Al 2 O 3 (k = 9), ZrO 2 (25), HfO 2 (25), TiO 2 (80), Y 2 O 3 (15), Ta 2 O 5 (22), LaZrO 2 (40), and CeO 2 (23)(24)(25)(26). It has observed that for suitable future scaling, a dielectric with k over 40 is preferred, and lanthanum doped zirconium oxide (LaZrO 2 ) has been considered as the promising high-k gate dielectric material for sub-22 nm node FinFET devices (Gaskell et al, 2007;Zhao et al, 2012;Liu et al, 2019;Cheng et al, 1999;Wikipedia 14nm process, 2020).…”