Numerical study of performance comparison between junction and junctionless thin-film transistors

Pai, C.H.; Lin, Jyi-Tsong; Wang, Shih‐Wei; Lin, Chien-Ku; Kuo, Yuan-Jui; Eng, Yi-Chuen; Lin, Po-Hsieh; Fan, Yi-Hsuan; Tai, Chih-Hsuan; Chen, Hsuan-Hsu; Chen, Cheng‐Hsin; Lu, Kuan-Yu

doi:10.1109/icsict.2010.5667600

Cited by 5 publications

(5 citation statements)

References 4 publications

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“…Although the SS value is relatively higher than the best value in single crystal silicon devices [15] and recent JLTs [20,43,44], it is still comparable with the lowest reported value of vertical silicon nanowire array devices [45]. In general, the degradation of SS is due to the increase in the interface state density, decrease of oxide capacitance, and increase in the doping concentration of metal oxide silicon transistor’s channel [46].…”

Section: Resultsmentioning

confidence: 99%

“…The most important reason for higher SS value in our case could be explained by the lack of oxide layer between the gate and the channel. It lacks the fixed potential drop in cross section of the nanowire (perpendicular to the current flow), which is necessary for inducing sufficient potential to change current linearly with the gate voltage [ 44 ]. In SGJLT device, the asymmetry of the gate location provides higher SS value compare to DGJLT device with the symmetric gate locations.…”

Section: Resultsmentioning

confidence: 99%

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Electrical property comparison and charge transmission in p-type double gate and single gate junctionless accumulation transistor fabricated by AFM nanolithography

et al. 2012

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The junctionless nanowire transistor is a promising alternative for a new generation of nanotransistors. In this letter the atomic force microscopy nanolithography with two wet etching processes was implemented to fabricate simple structures as double gate and single gate junctionless silicon nanowire transistor on low doped p-type silicon-on-insulator wafer. The etching process was developed and optimized in the present work compared to our previous works. The output, transfer characteristics and drain conductance of both structures were compared. The trend for both devices found to be the same but differences in subthreshold swing, ‘on/off’ ratio, and threshold voltage were observed. The devices are ‘on’ state when performing as the pinch off devices. The positive gate voltage shows pinch off effect, while the negative gate voltage was unable to make a significant effect on drain current. The charge transmission in devices is also investigated in simple model according to a junctionless transistor principal.

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Electrical property comparison and charge transmission in p-type double gate and single gate junctionless accumulation transistor fabricated by AFM nanolithography

et al. 2012

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“…It lacks the fixed potential drop in a cross-section of the nanowire (perpendicular to the current flow), which is required for inducing sufficient potential to change current linearly with the gate voltage [17]. The electric capacitance and polarisation in the gap between the channel and the gate, filled with air, is insufficient to provide the strong electric field and make the accumulation layer (because of low concentration).…”

Section: Methodsmentioning

confidence: 99%

Numerical investigation and comparison with experimental characterisation of side gate p-type junctionless silicon transistor in pinch-off state

et al. 2012

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A side gate p-type junctionless silicon transistor is fabricated by atomic force microscopy nanolithography using a anisotropic potassium hydroxide wet etching process on low doped (10 5 cm 23 ) silicon-on-insulator wafer. The structure is a gated resistor and turns off based on a pinch-off effect principle, when essential positive gate voltage is applied and made a sufficiently large barrier in the gating region. Negative gate voltage is unable to make a significant impact on drain current to drive the device into accumulation mode. The experimental transfer characteristic is investigated and compared with the simulation result for positive gate voltage. 'On/off' ratio and subthreshold swing were also measured. The numerical study of the device in 'off' state is investigated based on the variation of majority and minority carriers' density and recombination generation in the active region of the device, which offers more understanding of the device operation and also for previous works.

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“…It seems that the most important parameter which plays the key role here could be the capacitance between the gate and the channel. Smaller L G lacks the fixed potential drop in cross section of the channel (perpendicular to the current flow), which is necessary for inducing sufficient potential to change current linearly with the gate voltage [45]. This effect has been improved by increasing the gate length which suppresses the SS.…”

Section: Depletion Regimementioning

confidence: 99%

Effect of lateral Gate Design on the Performance of Junctionless Lateral Gate Transistors

et al. 2019

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In this paper, we investigate the effect of lateral gate design on performance of a p-type double lateral gate junctionless transistors (DGJLTs) with an air gate gap. The impact of lateral gate length, which modifies the real channel length of the device and gate gap variation down to 50 nm which have been found to be the most influential factors in the performance of the device have been comprehensively investigated. The characteristics are demonstrated and compared with a nominal DGJLTs through three-dimensional technology computer-aided design (TCAD) simulation. At constant channel geometry (thickness and width), when the lateral gate length decreases, the results show constant flatband drain current characteristics while the OFF state current (IOFF) increases significantly. On the other hand, by decreasing the air gap the subthreshold current considerably decreases while the flatband current is constant. Moreover, at a certain gate gap, the gates lose control over the channel and the device simply works as a resistor. Electric field component, carriers’ density, band edge energies, and recombination rate of the carriers inside the channel in depletion and accumulation regimes are analysed to interpret the variation of output characteristics.

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Numerical study of performance comparison between junction and junctionless thin-film transistors

Cited by 5 publications

References 4 publications

Electrical property comparison and charge transmission in p-type double gate and single gate junctionless accumulation transistor fabricated by AFM nanolithography

Electrical property comparison and charge transmission in p-type double gate and single gate junctionless accumulation transistor fabricated by AFM nanolithography

Numerical investigation and comparison with experimental characterisation of side gate p-type junctionless silicon transistor in pinch-off state

Effect of lateral Gate Design on the Performance of Junctionless Lateral Gate Transistors

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