O-band Energy-efficient Broadcast-friendly Interconnection Scheme with SiPho Mach-Zehnder Modulator (MZM) & Arrayed Waveguide Grating Router (AWGR)

Optics in Computing: From Photonic Network-on-Chip to Chip-to-Chip Interconnects and Disintegrated Architectures

“…This indicates that the onboard version has the credentials to lead to 63.3% reduction in energy compared to the 16.2 pJ/bit link energy efficiency of Intel QPI [134]. Energy efficiency can be additionally improved when incorporating a broadcast-friendly transceiver layout as has been already reported in [135], which can successfully handle the broadcasted traffic typically encountered during cache coherency updates in MSBs and often comprising up to 65% of the total traffic [101]. Finally, we report on how the optically-enabled MSBs can be beneficially employed in rack-scale disaggregated systems when equipped with an additional transceiver lane for dealing with the off-board traffic and are combined with the recently demonstrated Hipoλaos high-port switch architecture [79].…”

“…To this end, a potential on-board layout of the 40 Gb/s C2C interconnect will probably eliminate the need for SOAs in the transmission lines, turning C2C energy consumption into a parameter that depends solely on the power requirements of the RM and its respective electronic driver, the PD-TIA and the external LD that feeds the RM with the CW optical beam. Considering the employment of state-ofthe-art RM drivers [138] and assuming an LD with 6.1 dBm output power and a 10% wall-plug efficiency, the energy efficiency of the proposed 40 Gb/s C2C photonic link was estimated at 5.95 pJ/bit that increases to 6.25 pJ/bit when incorporating also state-of-the-art SerDes [139] , assuming a LD-to-RM coupling loss of 3dB [140], a RM insertion loss of 1.5 dB, 0.5dB for every Silicon-to-polymer and polymer-to-Silicon waveguide coupling [131] and an AWGR channel insertion loss of 6dB [135]. These energy efficiency values suggest a 63.3% and 61.4% improvement, respectively, compared to the 16.2 pJ/bit link energy efficiency of Intel QPI [134].…”

“…A more detailed description of the Hipoλaos architecture can be found in [78]. The Hipoλaos architecture can enable also the realization of multicast functionality, building upon the proven efficiency of AWGR devices in multicast operations [149], while its integration roadmap has already been reported in a preliminary 9×9 switch prototype exploiting μm SOI technology for the most challenging integration part, i.e. its Optical Delay Lines [80].…”

O-Band Silicon Photonic Transmitters for Datacom and Computercom Interconnects

“…The use of silicon photonics as the main technological platform across different DC hierarchical layers can certainly lead to reduced interconnection cost, but has to evolve along a versatile Si-TX technology that can address the rich variety of computing architectures spanning from on-chip through chip-to-chip and up to rack-to-rack configurations and their respective interconnection needs, including a) high line-rate and low-loss operation with low energy consumption, b) WDM operational credentials, c) multi-and broadcasting capabilities to comply with the multicast traffic characteristics in cache-coherent computational settings, like multi-socket layouts [26], d) tight packaging with electronic CMOS circuits and drivers (DR) to facilitate high-speeds at a low energy envelope, e) ideally sub-V driving voltage requirements to avoid the use of extra IC driver circuitry. Meeting this challenging framework has already revealed some important functional and performance benefits at system-level, with preliminary results outlining significant energy savings in multisocket board (MSB) systems when enabling different Tx operational modes [27]. Moreover, equipping O-band Si-TXs with WDM credentials can not only enable bandwidth scaling through parallel wavelength lanes, but can also lead to highly useful low-latency routing functions when combined with well-established Arrayed Waveguide Grating Router (AWGR)based interconnect architectures at all DC hierarchical layers [28]- [35], recently also demonstrated as integrated modules for O-band operation [33]- [34].…”

“…Finally, we present a TX subassembly prototype based on an integrated RM co-packaged with a low-power fullydepleted silicon-on-insulator (FDSOI) CMOS driver, operating at 50 Gb/s with a RM-driving voltage of only 1 V and 40 mW power consumption that yields a 0.8 pJ/bit energy efficiency. The functional and performance benefits of this versatile silicon TX technology portfolio can be highlighted in an all-to-all AWGR-based interconnect architecture for multisocket boards (MSBs), where each socket employs the whole set of constituent silicon TX building blocks and can switch between unicasting and multicasting operational modes offering important energy savings [27]. The latest promising developments of monolithically-integrated CMOS-compatible III/V-on-Si lasers with reduced coupling losses in O-band [37] could significantly pave the way to tighter integration of light sources together with the rest of TX circuitry with significant benefits on the functionality, performance and density.…”