OASIS vs. GDSII stream format efficiency

Reich, Alfred J.; Nakagawa, Kent H.; Boone, Robert

doi:10.1117/12.518271

Cited by 16 publications

(9 citation statements)

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“…GDSII and OASIS represent circuit features such as polygons and lines and describe them by their corner points. 6,8 GDSII and OASIS formatted data are far more compact than the uncompressed image of a circuit layer. Therefore it may initially appear that the GDSII and OASIS formats are good candidates for this particular application.…”

Section: Overviewmentioning

confidence: 99%

A lossless circuit layout image compression algorithm for electron beam direct write lithography systems

Yang

Savari

2011

Alternative Lithographic Technologies III

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The recent algorithm Corner is a transform-based technique to represent a circuit layout image for electron beam direct write lithography systems. We improve the lossless circuit layout compression algorithm Corner so that 1) it requires fewer symbols during the corner transform, 2) it has a simpler and faster decoding process, and 3) it requires a similar amount of memory for the decoding process.Conventional photolithography systems use physical masks, which are difficult to create and nearly impossible to modify. EBDW (Electron Beam Direct Write) lithography systems are an interesting alternative which bypass physical masks. 1 As illustrated in Figure 1, they instead utilize an electron beam writer to directly write a mask image on a photo-resist coated wafer. There are a number of advantages to EBDW lithography systems. First, the flexibility gained by replacing physical masks with electronic images makes EBDW lithography systems attractive when rapid prototyping is needed for the chip design process.Second, EBDW lithography systems have the potential to be improved by software because the mask images are electronically controlled. This last point will be the focus of this paper.However, EBDW lithography systems have a drawback over physical mask lithography systems: they are slow. 2, 3 A conventional photolithography system can produce the layout images for an entire wafer in one minute. 2 An EBDW lithography system can currently achieve this throughput for circuits with relatively large features, but not for circuits with smaller features because of insufficient bandwidth between the storage where the layer images are deposited and the EBDW lithography system.Dai and Zakhor 2, 4 used lossless image compression to address this problem. As shown in Figure 2, they cache compressed layout images in storage disks and send this compressed data to the processor board memory.Then the EBDW lithography system can be used for layout images with a higher resolution if the decoder embedded within the EBDW lithography writer can recover the original images from the compressed files quickly enough. This type of system has two requirements: 5 1) the compression ratio should be at least (Transfer rate of Decoder to Writer / Transfer rate of Memory to Decoder), and 2) the decoding algorithm must have low enough complexity to be a small addition to the EBDW lithography writer. This second constraint requires the use of a decoder operating with little memory.The layout images of memory cells typically display repeated patterns in contrast to the layout images of control logic circuits. The first lossless image compression algorithm, which is known as C4, 2 is based on context prediction and searching for repeated patterns within an image. Dai and Zakhor later introduced Block C4, 4 which significantly reduces the encoding complexity without sacrificing the compression ratio.

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Section: Overviewmentioning

confidence: 99%

A lossless circuit layout image compression algorithm for electron beam direct write lithography systems

Yang

Savari

2011

Alternative Lithographic Technologies III

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“…The SEMI standard P39 OASIS (Open Artwork System Interchange Standard) is the dominant format used to describe integrated circuit physical layouts. [15][16][17] Curvilinear intent is approximated in P39 using piecewise linear representation to form polygons. The number of edges used to represent the curvilinear intent is optimally determined by the accuracy required by downstream processes.…”

Section: Implementation Challenges Of Curvilinear Layoutsmentioning

confidence: 99%

Study on various curvilinear data representations and their impact on mask and wafer manufacturing

Choi

Ryu

Lee

et al. 2021

J. Micro/Nanopattern. Mats. Metro.

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“…Layout image data is commonly cached in GDSII [Rubin (1987)] or OASIS [Chen et al (2004)] formats. GDSII and OASIS describe circuit features such as polygons and lines by their corner points [see Rubin (1987) and Reich et al (2003)]. GDSII and OASIS formatted data are far more compact than the uncompressed image of a circuit layer.…”

Section: The Compression Algorithm 21 Overviewmentioning

confidence: 99%

Recent Advances in Nanofabrication Techniques and Applications

Cui¹

2011

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Recent Advances in Nanofabrication Techniques and ApplicationsRecent Advances in Nanofabrication Techniques and Applications Electron Beam Lithography for Fine Dot Arrays with Nanometer-Sized Dot and Pitch 9 EB-drawing system [7]I have already reported key technologies which enable ultrahigh packing over 1 Tb/in 2 : (1) the use of an EB drawing system with a fine probe and large probe current, (2) the thinning of the resist to prevent the spread of incident electron scattering in the resist, and (3) the design of a highly packed pattern with a hexagonal or centered rectangular lattice structure to avoid the proximity effect (Fig. 3. 1). The EB drawing system consists of a HR-SEM (JSM6500F, JEOL, Ltd.) and a writing controller (Tokyo Technology Co., Ltd.) (Fig. 3. 2). The drawing was done on a resist coating on a piece of Si placed on the XY table, which was not moved during the EB writing. This type system is very suitable for checking the limit of the drawing pattern size, because the stage position error can be neglected. The system provides a high probe current of 2 nA at a resolution of 2 nm. We used the system under a probe current of 100 pA and an acceleration voltage of 30 kV. In the drawing, the address resolutions were 10 nm and 2.5 nm for ZEP520 and calixarene [14, 15] resists, respectively. Development was carried out using the commercial developers ZED-N50 (MIBK+IPA) and ZEP-RD (xylene) for 210 sec and 180 sec for ZEP520 and calixarene, respectively. In particular, we adjusted the focus to get the fine probe on the sample surface at a magnification of 250k-200k. In order to achieve 1-Tb/in 2 storage patterned media, we carried out experiments to confirm whether EB writing can form very fine pit or dot arrays with a pitch of <60 nm or not. At first, we coated the resist on a piece of Si substrate with a thickness of 70 nm and 15 nm in ZEP520 and calixarene, respectively. After pre-baking, we drew ultrahigh-packed pit and dot patterns with a pitch of 20-60 nm. After developing and rinsing the resists, we checked the drawn patterns using the same HR-SEM. Thinning allows not only to prevent electron scattering extension in the resist, but also to avoid electron charging. We determined the minimum thickness at which there is sufficient contrast and no damage to the resist during SEM observation. The thickness of 70 nm in ZEP520 resist was decided by electron damage and contrast signal in SEM. I could not obtain the high magnitude SEM image in a thickness range of less than 70 nm.Recent Advances in Nanofabrication Techniques and Applications 10 3.2 EB drawing [7, 13] 3.2.1 Using ZEP520 positive EB resist Figure 3.3 shows SEM images of ZEP520 pit patterns drawn at an exposure dosage of around 180 C/cm 2 . The figure shows that the minimum pit arrays were drawn with a minimum pit diameter of <20 nm at a pitch of 40 nm x 60 nm [13]. We could not form higherpacked pit patterns than this. Furthermore, the pit size drastically changed, with a fluctuation of about 18 nm in this pitch arrays pattern and about 11 ...

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OASIS vs. GDSII stream format efficiency

Cited by 16 publications

References 0 publications

A lossless circuit layout image compression algorithm for electron beam direct write lithography systems

A lossless circuit layout image compression algorithm for electron beam direct write lithography systems

Study on various curvilinear data representations and their impact on mask and wafer manufacturing

Recent Advances in Nanofabrication Techniques and Applications

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