Chemical-mechanical polishing (CMP) is an enabling technique used in deep-submicron VLSI manufacturing to achieve uniformity in long range oxide planarization [1]. Post-CMP oxide topography is highly related to local spatial pattern density in layout. To change local pattern density, and thus ensure post-CMP planarization, dummy features are placed in layout. Based on models that accurately describe the relation between local pattern density and post-CMP planarization [7; 5; 9], a two-step procedure of global density assignment followed by local insertion is proposed to solve the dummy feature placement problem in the fixeddissection regime with both single-layer and multiple-layer considerations. Two experiments, conducted with real design data, gave excellent results by reducing post-CMP topography variation from 767Å to 152Å in the single-layer formulation and by avoiding cumulative effect in the multiple-layer formulation. The result from single-layer formulation compares very favorably both to the rulebased approach widely used in industry and to the algorithm in [3]. The multiple-layer formulation has no previously published work.

As lithography and other patterning processes become more complex and more non-linear with each generation, the task of physical design rules necessarily increases in complexity also. The goal of the physical design rules is to define the boundary between the physical layout structures which will yield well from those which will not. This is essentially a rule-based pre-silicon guarantee of layout correctness. However the rapid increase in design rule requirement complexity has created logistical problems for both the design and process functions [1]. Therefore, similar to the semiconductor industry's transition from rule-based to model-based optical proximity correction (OPC) due to increased patterning complexity, opportunities for improving physical design restrictions by implementing model-based physical design methods are evident. In this paper we analyze the possible need and applications for model-based physical design restrictions (MBPDR). We first analyze the traditional design rule evolution, development and usage methodologies for semiconductor manufacturers. Next we discuss examples of specific design rule challenges requiring new solution methods in the patterning regime of low K1 lithography and highly complex RET. We then evaluate possible working strategies for MBPDR in the process development and product design flows, including examples of recent model-based pre-silicon verification techniques [2]. Finally we summarize with a proposed flow and key considerations for MBPDR implementation.

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