OASYS: a framework for analog circuit synthesis

Abstract

We describe a hierarchical structure for a knowledge-based analog circuit synthesis tool. Analog circuit topologies are represented as a hierarchy of abstract functional blocks each with associated design knowledge. We also describe mechanisms to select from among alternate design styles, and to translate performance specifications from one level in the hierarchy to the next lower level. A prototype implementation, OASYS, synthesizes sized transistor schematics for CMOS operational amplifiers and comparators from a set of performance specifications and process parameters. We describe the role such a synthesis system can play in exploring the space of designable circuits. And finally, we briefly describe other related research in analog synthesis at Carnegie Mellon, including OASYS-VM, which facilitates the addition of new design topologies to the framework, and ANAGRAM, the counterpart to OASYS, which performs the circuit schematic to physical layout phase of analog circuit design Functional Specifications

Design of Analog Integrated Circuits using Simulated Annealing/Quenching with Crossovers and Particle Swarm Optimization

“…Initial studies in circuit level synthesis were done in the 1980's and were mostly knowledge-based approaches [5], [10]. These approaches tried to capture the design knowledge required to perform some circuit implementation and implement it in algorithms.…”

Simulated Annealing to Improve Analog Integrated Circuit Design: Trade-Offs and Implementation Issues

“…Previous works have been done in the field of analog design automation to enable fast design at the block level. Different strategies and approaches have been proposed during the evolution of analog design automation, such as simulation-based optimization [5,9,17], symbolic simulation [10], artificial intelligence [6], manually derived design equations [4,21], hierarchy and topology selection [11], geometric programming [12,16] and memetic algorithms [15]. The main difficulty encountered for wide spread usage of these tools is that they require appropriate modeling of both devices (technology dependent) and circuit topologies in order to achieve the design objectives in a reasonable processing time.…”

A flexible design methodology for analog test wrappers in mixed-signal SOCs

“…Several analog synthesis tools have also been developed [15,16]. The availability of well-developed and automated design and synthesis tools has made the integration of on-chip data converters feasible.…”