Observability solutions for in-field functional test of processor-based systems: A survey and quantitative test case evaluation

Acle, Julio Pérez; Cantoro, Riccardo; Hailemichael, A.T.; Sánchez, Ernesto; Reorda, M. Sonza

doi:10.1016/j.micpro.2016.09.002

Cited by 9 publications

(5 citation statements)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The approach mimics what has been done in the recent past for microcontrollers and SoCs (by adding embedded instruments to be used for design validation, silicon debug, and test) and was extended to PCBs, taking advantage of the existence of software accessible embedded instruments that can significantly improve the fault observability. We also investigated the usage of other instruments, corresponding for example to the debug infrastructure [DU16] and performance counters which are present in many microprocessors [PER16], to better support functional test. Finally, the BASTION partners successfully investigated new solutions to increase the effectiveness of functional test programs [PER16] and to automate the generation of functional programs for testing permanent faults in small-and medium-sized processors [RIE16].…”

Section: Instrument-assisted Testing For Nffmentioning

confidence: 99%

“…We also investigated the usage of other instruments, corresponding for example to the debug infrastructure [DU16] and performance counters which are present in many microprocessors [PER16], to better support functional test. Finally, the BASTION partners successfully investigated new solutions to increase the effectiveness of functional test programs [PER16] and to automate the generation of functional programs for testing permanent faults in small-and medium-sized processors [RIE16].…”

Section: Instrument-assisted Testing For Nffmentioning

confidence: 99%

See 1 more Smart Citation

BASTION: Board and SoC test instrumentation for ageing and no failure found

Jutman¹,

Lotz²,

Larsson

et al. 2017

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2017

View full text Add to dashboard Cite

This is an overview paper that motivates and describes performed work done in the European Commission funded research project BASTION, which focuses on two critical problems of modern electronics: the No-Fault-Found (NFF) and CMOS ageing. New defect classes contributing to NFF have been identified, including timing related faults (TRF) at board level and intermittent resistive faults (IRF) at IC level. BASTION has addressed the mechanisms of ageing and developed several techniques to improve the longevity of electronic products. Embedded Instrumentation, monitors, and IEEE 1687 standard for reconfigurable scan networks (RSN) are seen as an important leverage that helped mitigating the impact of the above listed problems by facilitating a low-latency, scalable online system health monitoring and error localization infrastructure as well as integration of all heterogeneous technologies into a homogeneous demonstration platform. This paper helps the reader to get a general overview of the work performed and provides a collection of references to publications where the respective research results are described in detail.

show abstract

Section: Instrument-assisted Testing For Nffmentioning

confidence: 99%

Section: Instrument-assisted Testing For Nffmentioning

confidence: 99%

BASTION: Board and SoC test instrumentation for ageing and no failure found

Jutman¹,

Lotz²,

Larsson

et al. 2017

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2017

View full text Add to dashboard Cite

show abstract

“…However, developing STLs from scratch is not a trivial task, more so when targeting delay faults on complex devices. For test programs to achieve high fault coverage figures, they must be able to excite as many faults as possible from the whole DUT and make their effects observable at primary outputs (POs) by using instructions from the system's instruction set architecture, only [20]. Achieving this requires a nonnegligible amount of manual effort by the test engineer.…”

Section: Introductionmentioning

confidence: 99%

Effective techniques for automatically improving the transition delay fault coverage of Self-Test Libraries

Cantoro

Garau

Girard

et al. 2022

2022 IEEE European Test Symposium (ETS)

View full text Add to dashboard Cite

In-field test of integrated circuits using Self-Test Libraries (STLs) is a widely used technique specifically suited to guarantee the processor's correct behavior during the operative lifetime, as mandated by functional safety standards such as ISO26262. Developing STLs for stuck-at faults requires significant manual efforts from test engineers, and targeting delay faults is even more challenging. In order to support this process, in this paper we propose a method to automate the creation of STLs targeting delay faults starting from existing STLs targeting stuck-at faults. The method is based first on identifying excited but not-observed transition delay faults and then adding suitable instructions able to observe (and hence detect) them. Experimental results on a RISC-V processor show that the method can systematically detect a significant percentage of the target faults with reasonable computational effort and test code size increase.

show abstract

“…However, developing STLs from scratch is not a trivial task and requires a non-negligible amount of manual effort, more so when targeting complex devices: test programs must be able to excite as many faults as possible and make their effects observable at primary outputs (POs) by using instructions from the system's instruction set, only [20]. Moreover, understanding why certain faults are not detected is not always easy.…”

Section: Introductionmentioning

confidence: 99%

Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage Improvement

Cantoro

Girard

Masante

et al. 2021

2021 IEEE 27th International Symposium on on-Line Testing and Robust System Design (IOLTS)

View full text Add to dashboard Cite

Testing digital integrated circuits is generally done using Design-for-Testability (DfT) solutions. Such solutions, however, introduce non-negligible area and timing overheads that can be overcome by adopting functional solutions. In particular, functional test of integrated circuits plays a key role when guaranteeing the device's safety is required during the operative lifetime (in-field test), as required by standards like ISO26262. This can be achieved via the execution of a Self-Test Library (STL) by the device under test (DUT). Nevertheless, developing such test programs requires a significant manual effort, and can be non-trivial when dealing with complex modules. This paper moves the first step in defining a generic and systematic methodology to improve transition delay faults' observability of existing STLs. To do so, we analyze previously devised STLs in order to highlight specific points within test programs to be improved, leading to an increase in the final fault coverage.

show abstract

Observability solutions for in-field functional test of processor-based systems: A survey and quantitative test case evaluation

Cited by 9 publications

References 15 publications

BASTION: Board and SoC test instrumentation for ageing and no failure found

BASTION: Board and SoC test instrumentation for ageing and no failure found

Effective techniques for automatically improving the transition delay fault coverage of Self-Test Libraries

Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage Improvement

Contact Info

Product

Resources

About