Observation of peripheral charge induced low frequency capacitance-voltage behaviour in metal-oxide-semiconductor capacitors on Si and GaAs substrates

Abstract

We report on experimental observations of room temperature low frequency capacitance-voltage (CV) behaviour in metal oxide semiconductor (MOS) capacitors incorporating high dielectric constant (high-k) gate oxides, measured at ac signal frequencies (2 kHz to 1 MHz), where a low frequency response is not typically expected for Si or GaAs MOS devices. An analysis of the inversion regions of the CV characteristics as a function of area and ac signal frequency for both n and p doped Si and GaAs substrates indicates that the source of the low frequency CV response is an inversion of the semiconductor/high-k interface in the peripheral regions outside the area defined by the metal gate electrode, which is caused by charge in the high-k oxide and/or residual charge on the high-k oxide surface. This effect is reported for MOS capacitors incorporating either MgO or GdSiOx as the high-k layers on Si and also for Al2O3 layers on GaAs(111B). In the case of NiSi/MgO/Si structures, a low frequency CV response is observed on the p-type devices, but is absent in the n-type devices, consistent with positive charge (>8 × 1010 cm−2) on the MgO oxide surface. In the case of the TiN/GdSiOx/Si structures, the peripheral inversion effect is observed for n-type devices, in this case confirmed by the absence of such effects on the p-type devices. Finally, for the case of Au/Ni/Al2O3/GaAs(111B) structures, a low-frequency CV response is observed for n-type devices only, indicating that negative charge (>3 × 1012 cm−2) on the surface or in the bulk of the oxide is responsible for the peripheral inversion effect.

Effective reduction of trap density at the Y2O3/Ge interface by rigorous high-temperature oxygen annealing

“…The corresponding measured data of the MOSCAPs are shown in Table I. It is noted that reliable IV and breakdown voltage measurements were hardly possible for the samples without PMA and the corresponding entries are marked by "…" in Table I. Generally, by varying the oxygen annealing temperature from 400 C to 550 C and 600 C, a large impact of temperature on CV characteristics becomes visible, reducing the D it by more than one order of magnitude from D it ¼ 3.7 Â 10 12 eV À1 cm À2 (400 C) to D it ¼ 1.24 Â 10 11 eV À1 cm À2 (550 C), and D it ¼ 9.7 Â 10 10 eV À1 cm À2 (600) C. As shown from the inversion regions of the CV curves in Figure 1, also an impact of annealing temperature on the minority response time is visible either induced by defects [36][37][38] or by peripheral inversion regions surrounding the metal gate pads as reported by Connor et al 39 The hystereses are remarkably low and vary in a range of 0.36 V (550 C) and <0.1 V (500 C) as depicted in Table I. If compared to the as deposited sample ( Fig.…”

Observation of Crystalline Oxidized Silicon Phase

“…The capacitor measurements reveal the presence of fixed positive charge in the crystalline preoxidized samples. This positive charge in fact compensates the negative charge of HfO 2 that causes an inherent hole inversion layer at the reference sample without the preoxidation (Figure c) . The formation of fixed positive charge in crystalline SiOx/Si is however well consistent with the intrinsic property of SiO x : it contains positively charged ions in relation to the covalent‐character charge states in the pure Si crystal, providing simultaneously an extra evidence for the unveiled SiO x /Si phase here.…”

Hysteresis in As-Synthesized MoS2 Transistors: Origin and Sensing Perspectives

“…In our previous work, we carried out an initial study in this regard, attributing this phenomenon to substrate limitations to reach the inversion layer at the back interface (SiO 2 /Si) due to the low doping level [32]. This limitation could be mitigated by peripheral inversion, a coupling effect, which usually happens in semiconductor devices when leaving regions exposed to ambient conditions or when there are residual charge on oxide surfaces [44]. If the density of the residual charge is higher than the semiconductor charge associated with the maximum depletion width, this charge may result in the depletion of the semiconductor surface and the generation and recombination of minority carriers.…”