Observation of source-to-drain direct tunneling current in 8 nm gate electrically variable shallow junction metal–oxide–semiconductor field-effect transistors

Abstract

Articles you may be interested inA detailed coupled-mode-space non-equilibrium Green's function simulation study of source-to-drain tunnelling in gate-all-around Si nanowire metal oxide semiconductor field effect transistors Model of random telegraph noise in gate-induced drain leakage current of high-k gate dielectric metal-oxidesemiconductor field-effect transistors Appl. Phys. Lett. 100, 033501 (2012); 10.1063/1.3678023 Analytical approach to integrate the different components of direct tunneling current through ultrathin gate oxides in n-channel metal-oxide-semiconductor field-effect transistors J. Appl. Phys. 93, 1064 (2003); 10.1063/1.1527710 On-off switching of edge direct tunneling currents in metal-oxide-semiconductor field-effect transistors Appl. Phys. Lett. 81, 3488 (2002); 10.1063/1.1518563Fabrication of 30 nm gate length electrically variable shallow-junction metal-oxide-semiconductor field-effect transistors using a calixarene resist

Scaling properties of the tunneling field effect transistor (TFET): Device and circuit

“…The TFET shows a much larger barrier compared to the MOSFET. For short-channel length an additional leakage path is expected for the MOSFET due to direct tunneling through the MOSFET barrier in the off-state [11]. This leakage mechanism does not exist for the TFET.…”

Silicon-Germanium Structure in Surrounding-Gate Strained Silicon Nanowire Field Effect Transistors

“…However, this approach is computationally expensive in the simulation of twoand three-dimensional (2D/3D) devices [14][15][16][17][18][19][20][21][22][23]. Phenomenological quantum correction model, a calibrated 3D density-gradient drift-diffusion model, is adopted in this work [14][15][16][17][18][19][20][21][22][23]. This approach quantitatively predicts the main tendency of electrical characteristics of the examined devices.…”

“…They have better transport characteristics and improved short channel effects (SCEs) than that of single gate (SG) strained FETs . On the other hand, pure Si-based surroundinggate FET has the best channel controllability and lowest SCEs among different structures of FETs [11][12][13][14][15][16][17][18][19][20][21][22][23]. We believe that study on surrounding-gate strained Si FETs can quantitatively provide rich information for diverse applications of nanodevice.…”

The Evolution of Theory on Drain Current Saturation Mechanism of MOSFETs from the Early Days to the Present Day

“…Since the tunneling probability increases exponentially with decreasing potential barrier width, a decrease in the gate length will significantly increase the direct S/D tunneling and thus increase the subthreshold current (Kawaura & Baba, 2003). Fortunately, the tunneling current will only exceed the thermal current and degrade the subthreshold slope when the gate length is less than 5 nm (experimentally 4 nm and theoretically 6 nm) (Kawaura et al, 2000). Therefore, we only need to be concerned with thermionic emission between the source and the drain for the state-of-the-art MOS transistors (L ≥ 32 nm).…”

“…SEMATECH has developed their 16 nm CMOS technology using high-K/metal gate (Huang et al, 2009). Furthermore, several research groups have already reported on the development of 10 nm planar bulk MOS transistors (Wakabayashi et al, 2004;Wakabayashi et al, 2006;Kawaura et al, 2000). It has been reported using a hypothetical double-gate MOS transistor that a direct source-drain (S/D) tunneling sets an ultimate scaling limit for transistor with gate length below 10 nm (Jing & Lundstrom, 2002).…”