Silicon-Germanium Structure in Surrounding-Gate Strained Silicon Nanowire Field Effect Transistors

Li, Yiming; Lee, Jam Wem; Chou, Hung Mu

doi:10.1007/s10825-004-7056-7

Cited by 6 publications

(9 citation statements)

References 21 publications

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“…Outside the channel, the level of source/drain doping is 3 × 10 20 cm −3 . Threedimensional drift-diffusion equations coupled with densitygradient quantum correction [33][34][35][36] are numerically solved to obtain the characteristics of the device [19][20][21] in the established parallel computing system [37][38][39]. A carefully calibrated density-gradient model [41,42] has attracted more and more attention, and successfully demonstrates its validity for efficient modeling of the quantum mechanical effects in a device simulation program using first-order quantum corrections [33][34][35][36].…”

Section: The Nanowire Fet Circuit and Simulation Methodologymentioning

confidence: 99%

DC baseband and high-frequency characteristics of a silicon nanowire field effect transistor circuit

Li¹,

Hwang²

2009

Semicond. Sci. Technol.

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Silicon-based nanowire field effect transistors (FETs) are potentially next-generation candidates for achieving high-performance targets of the International Roadmap for Semiconductors due to their superior reduction of the short-channel effects and excellent compatibility with planar complementary metal oxide semiconductor (CMOS) fabrication process. In this work, we for the first time numerically explore the dc baseband and high-frequency characteristics, and the design of the device aspect ratio (channel length/channel thickness) for the silicon nanowire FET circuits by using a three-dimensional device/circuit-coupled mixed-mode simulation technique. With the experimentally validated simulation approach, the result shows the rather prolific dc baseband and high-frequency properties of silicon-based nanowire FET devices as active components. In design of silicon nanowire FETs, taking the nanowire's radius and channel length as two crucial factors, the demands of the device aspect ratio on dc characteristics are found to be inversely proportional to the demands of the high-frequency characteristics. Therefore, to compromise both the dc and high-frequency characteristics, the design margin of the device aspect ratio restricted, in which the requirements of dc and high-frequency characteristics provide aspect ratio upper and lower bounds, respectively. Moreover, the design margin will be more tightened for a device with larger radius due to the weakened channel controllability. The extensive results and analyses are presented for the promising devices for the design of high-frequency analog applications.

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Section: The Nanowire Fet Circuit and Simulation Methodologymentioning

confidence: 99%

DC baseband and high-frequency characteristics of a silicon nanowire field effect transistor circuit

Li¹,

Hwang²

2009

Semicond. Sci. Technol.

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“…With the results of the 3D process simulation, a simplified doping profile is used in the 3D simulation of the 25 nm device. The device simulation is performed by solving a hydrodynamic model for electron, which is coupled with the density-gradient equations to include the quantum mechanical effects [7,9]. The coupled device equations are firstly decoupled according to Gummel's method.…”

Section: Computational Modelmentioning

confidence: 99%

“…The fin height is equal to 37.5 nm and the fin width is set to be 25 nm. We note that the ratio of the channel and the silicon fin width is equal to 1, which satisfies the optimal ratio (>2/3) [9,12,13]. The devices have polysilicon gates, so the work function of 4.17 eV is introduced.…”

Section: Computational Modelmentioning

confidence: 99%

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Numerical simulation and comparison of electrical characteristics between uniaxial strained bulk and SOI FinFETs

2006

J Comput Electron

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In this paper, electrical characteristics of 25 nm strained fin-typed field effect transistors (FinFETs) with oxide-nitride-stacked-capping layer are numerically studied. The FinFETs are fabricated on two different wafers, one is bulk silicon and the other is silicon-on-insulator (SOI) substrate. A three-dimensional device simulation is performed by solving a set of density-gradient-hydrodynamic equations to study device performance including, such as the drain current characteristics (the I D -V G and I D -V D curves), the drain-induced barrier height lowering, and the subthreshold swing. Comparison between the strained bulk and SOI FinFETs shows that the strained bulk FinFET is promising for emerging multiple-gate nanodevice era according to the manufacturability point of view.

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“…The channel and source/drain doping concentrations of the designed device are 2 × 10 17 cm −3 and 3 × 10 20 cm −3 , respectively. Notably, to sustain favorable operating characteristics, the ratio of channel Common Source Amplifier Inverter length (L g ) to the thickness (T si ) of the surrounding-gate device should exceed 1 [19,21]. In this investigation, the ratio of the channel length to the thickness is fixed at 1.6, satisfying the design criteria for silicon surrounding-gate transistors.…”

Section: Introductionmentioning

confidence: 99%

The effect of the geometry aspect ratio on the silicon ellipse-shaped surrounding- gate field-effect transistor and circuit

Hwang

2009

Semicond. Sci. Technol.

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The silicon (Si) surrounding-gate metal-oxide-semiconductor field-effect transistor (MOSFET) has ultimate gate structures and is a potential candidate for use in next-generation high-performance nano-devices. However, because of limitations of the fabrication process, theoretically ideally round shape of the surrounding gate may not always guarantee. These limitations may lead to the formation of an ellipse-shaped surrounding gate with major (a) and minor (b) axes of different lengths. In this study, the effect of the geometry aspect ratio, a/b, on the dc and ac characteristics of the 16 nm gate ellipse-shaped surrounding-gate MOSFETs and circuits is examined by using a three-dimensional coupled device-circuit simulation technique. The dependences of electrical characteristics on the geometry aspect ratio are evaluated with reference to various device characteristics and the circuit properties, including the circuit gain, the 3 dB bandwidth, the unity-gain bandwidth, the rise/fall time and the delay time. In analog circuits, the device with an aspect ratio of less than 1 is promising because the short-channel effect is suppressed. However, for a digital circuit configuration, the transient response of the circuit relies on the charge/discharge capability of the transistor. Thus, a device with a large aspect ratio, such as 2, will be more suitable for digital applications.

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Silicon-Germanium Structure in Surrounding-Gate Strained Silicon Nanowire Field Effect Transistors

Cited by 6 publications

References 21 publications

DC baseband and high-frequency characteristics of a silicon nanowire field effect transistor circuit

DC baseband and high-frequency characteristics of a silicon nanowire field effect transistor circuit

Numerical simulation and comparison of electrical characteristics between uniaxial strained bulk and SOI FinFETs

The effect of the geometry aspect ratio on the silicon ellipse-shaped surrounding- gate field-effect transistor and circuit

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