Obstacle-free two-dimensional online-routing for run-time reconfigurable FPGA-based systems

Abstract

By neatly reserving routing resources of an FPGA at design-time, a circuit switching network can be implemented for integrating reconfigurable modules in a two-dimensional manner at run-time. In this network, paths can be set directly by manipulating fractions of the switch matrix configuration. By utilizing disjoint resources for implementing the network and the modules of the system, the network is capable to route paths to partial modules independent of the present module placement layout. This paper proposes concepts, implementation issues, and a design flow for building reconfigurable systems providing such a network. Furthermore, a timing model will be presented for validating the system at run-time. The applicability of the network will be demonstrated in a prototype system by routing I/O pins to partial modules.

Microkernel Architecture and Hardware Abstraction Layer of a Reliable Reconfigurable Real-Time Operating System (R3TOS)

“…Especially interesting is the work described in , where the authors propose to emulate a NoC by harnessing the reconfiguration mechanism of the FPGA. The possibility of creating online routes among the tasks has also been proposed [Suris et al 2008;Koch et al 2010], but its acceptance is low due to the long time overheads when creating the routes, and difficulties when dealing with FPGA configuration, whose format is not documented. Therefore, most of currently available ROSes rely on a static communication infrastructure which interconnects all of the reconfigurable slots in the system, where the hardware tasks are allocated, and the main processor, where the software part of the OS runs, e.g.…”