Obtaining Temporal and Timed Properties of Logic Controllers From Fault Tree Analysis

Abstract

One of the prerequisites for formal verification of logic controllers using modelchecking is the formalization of properties to verify. The work presented in this paper proposes a method to elaborate the formal properties of a logic controller from a Fault Tree Analysis (FTA). The method developed here extends the traditional FTA with event ordering and timed information by introducing specific gates which model logic and physical time constraints. The behavior of these gates is then formalized in the form of state automata; formal properties are derived from the set of automata obtained at the end of FTA. A simple case study exemplifies the method.

Formal Verification of Complex Systems based on SysML Functional Requirements

“…These local properties are subsequently verified for each component. However, Barragan et al (Barragan, Roth, Faure, et al, 2006) emphasizes the difficulty of transforming the global system requirements into multi-level sub-system and component's local safety properties that need to be verified by a model checker for the design of large scale complex engineered systems. More specifically, the decomposition of complex engineered systems into multi-domain sub-systems involving electrical, mechanical, and software components makes the refinement and traceability of the global safety properties very difficult.…”