OCCN: a network-on-chip modeling and simulation framework

Coppola, Marcello; Curaba, Stephane; Grammatikakis, Miltos D.; Maruccia, Giuseppe; Papariello, Francesco

doi:10.1109/date.2004.1269226

Cited by 37 publications

(22 citation statements)

References 12 publications

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“…Coppola et al [12] present OCCN, a framework for modeling and simulation of communication infrastructures which enables defining protocols, master and slave port behavior and statistical packages. However, OCCN does not support description of architectural details of the communication environment.…”

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Integrating Abstract NoC Models within MPSoC Design

Moreno

Popovici

Calazans

et al. 2008

2008 the 19th IEEE/IFIP International Symposium on Rapid System Prototyping

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Current embedded applications are migrating from single processor-based systems to intensive data communication requiring multiprocessing. The performance demanded by these applications requires the use of heterogeneous multiprocessing architectures in a single chip (MPSoCs) endowed with complex communication infrastructures, such as Networks on Chip or NoCs. NoC parameter choices, such as network dimensioning, topology, routing algorithm, and buffer sizing then become essential aspects for optimizing the implementation of such complex systems. This paper presents NoC models that allow evaluating communication architectures through the variation of parameters during MPSoC design. Applicability of the concepts is demonstrated through two heterogeneous MPSoC case studies: an MJPEG decoder and an H.264 encoder. IntroductionMultiprocessor SoCs (MPSoCs) are emerging as one of the technologies providing a way to face the growing design complexity of embedded systems, since they provide flexibility of programming allied to specific processor architectures adapted to selected problem classes. This leads to gains in compactness, low power consumption and performance [1][2]. MPSoCs integrate hardware (HW) such as processors, memories, interconnect and special purpose modules and software (SW) like operating systems and application code. MPSoC design is usually platform-based and dominated by SW design, to achieve cost and time efficiency [3]. The amount of functionality incorporated in an MPSoCs is continuously growing. Consequently, their complexity and size also increases. Therefore, on chip communication demands rise. Industry roadmaps and research literature point that communication will be the greater challenge in future MPSoC projects, representing up to 50% of the total energy consumption, thus becoming the system performance bottleneck [4]. The way an application is partitioned and the employed communication structures directly affect system energy and performance figures. This paper proposes a flow for inserting NoC design considerations during MPSoC design. This is achieved through communication architecture model parameterization and simulation with the target application. This flow makes use of three distinct abstraction levels to model application functionality together with the hardware architecture, and allows analyzing performance for varying NoC parameters. Among NoC parameters that can be varied stand the number of routers, the routing algorithm and the MPSoC IP cores mapping on the NoC. The main contribution of this paper is the definition of abstract NoC models that can be integrated into MPSoC design flows and the demonstration of the utility of such models through the use of two real world case studies, an MJPEG decoder and an H.264 encoder.The paper is organized as follows. Section 2 presents related work in MPSoC communication modeling and evaluation. Section 3 depicts the proposed flow, and the proposed NoC models. Section 4 presents the conducted experiments, while Section 5 discusses re...

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Section: Related Workmentioning

confidence: 99%

“…Xu et al [14] [12] for all the communication models. Some statistical information is captured by the flow.…”

Section: Related Workmentioning

confidence: 99%

Integrating Abstract NoC Models within MPSoC Design

Moreno

Popovici

Calazans

et al. 2008

2008 the 19th IEEE/IFIP International Symposium on Rapid System Prototyping

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“…(9) Genko et al [43] present a flexible emulation environment implemented on an FPGA that is suitable to explore, evaluate, and compare a wide range of NoC solutions with a very limited effort. (10) Coppola et al [44] proposes an efficient, open-source research and development framework (On-Chip Communication Network (OCCN)) for the specification, modeling, and simulation of on-chip communication architectures. (11) Zeferino and Susin [45] present SoCIN, a scalable network based on a parametric router architecture to be used in the synthesis of customized low cost NoCs.…”

Section: Mpsoc Design Literature Reviewmentioning

confidence: 99%

Framework for Simulation of Heterogeneous MpSoC for Design Space Exploration

Tafesse

Muthukumar

2013

VLSI Design

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Due to the ever-growing requirements in high performance data computation, multiprocessor systems have been proposed to solve the bottlenecks in uniprocessor systems. Developing efficient multiprocessor systems requires effective exploration of design choices like application scheduling, mapping, and architecture design. Also, fault tolerance in multiprocessors needs to be addressed. With the advent of nanometer-process technology for chip manufacturing, realization of multiprocessors on SoC (MpSoC) is an active field of research. Developing efficient low power, fault-tolerant task scheduling, and mapping techniques for MpSoCs require optimized algorithms that consider the various scenarios inherent in multiprocessor environments. Therefore there exists a need to develop a simulation framework to explore and evaluate new algorithms on multiprocessor systems. This work proposes a modular framework for the exploration and evaluation of various design algorithms for MpSoC system. This work also proposes new multiprocessor task scheduling and mapping algorithms for MpSoCs. These algorithms are evaluated using the developed simulation framework. The paper also proposes a dynamic fault-tolerant (FT) scheduling and mapping algorithm for robust application processing. The proposed algorithms consider optimizing the power as one of the design constraints. The framework for a heterogeneous multiprocessor simulation was developed using SystemC/C++ language. Various design variations were implemented and evaluated using standard task graphs. Performance evaluation metrics are evaluated and discussed for various design scenarios.

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“…A similar approach was presented by Kogel et al [9], with data processed at transaction level by a network engine that can implement high-level behaviour of point-to-point, bus-based, and crossbar interconnects. Coppola et al [10] presented OCCN, a modeling and simulation framework that features a layered model for inter-module communication, with each layer translating transaction requests to a lower-level protocol.…”

Section: Related Workmentioning

confidence: 99%

A flexible network-on-chip simulator for early design space exploration

Grecu¹,

Ivanov²,

Saleh³

et al. 2008

2008 1st Microsystems and Nanoelectronics Research Conference

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Abstract-The communication requirements of large multi-core systems are convened by on-chip communication fabrics generally referred to as networks-on-chip (NoC). We have designed a simulation environment that allows early exploration of the performance and cost parameters of network-on-chip communication architectures, which is able to handle arbitrary topologies and routing schemes. The simulator implements a flit-level message-passing mechanism and supports application data specified as input trace files or generated at run-time by synthetic traffic generators.

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OCCN: a network-on-chip modeling and simulation framework

Cited by 37 publications

References 12 publications

Integrating Abstract NoC Models within MPSoC Design

Integrating Abstract NoC Models within MPSoC Design

Framework for Simulation of Heterogeneous MpSoC for Design Space Exploration

A flexible network-on-chip simulator for early design space exploration

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