Offloading Collective Operations to Programmable Logic on a Zynq Cluster

Arap, Omer; Swany, Martin

doi:10.1109/hoti.2016.024

“…This approach rst calls the barrier collective communication operation to synchronize all nodes, and then the reduce-all collective communication operation to complete the GALT operation [13]. Field programmable gate arrays (FPGAs) have been employed to enhance the operation of collective communication [14], [15].…”

Section: Related Workmentioning

confidence: 99%

Network accelerator for parallel discrete event simulations

Karaca

¹

,

İmre

²

,

Alkar

³

2023

J Supercomput

0

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The simulation time of parallel and distributed discrete event simulation is the heart rate for as-fast-as execution schemes. Agreeing upon a global simulation time and distributing it to the simulation processes can be improved by exploiting or redesigning the network hardware. In this paper, we present such an approach that o oads simulation time calculations to network switches in order to speed up the steps where time advance requests are made and time advance grants are waited. By reducing the waiting time for time advancement, we aim to improve the overall performance of the parallel simulations. The measurements from the FPGA-based hardware setup and the results from our network simulations show that overall performance can be improved when time management calculations are o oaded to the network switches. Additionally, the transient message problem is also solved within the network by not allowing the time control messages to bypass the time-dependent events. The network acceleration of the region-based event distribution is also studied, and o oading the region matching tasks to the network switches is found to be feasible to reduce the costs of node-based calculations, especially for fast-moving regions. In this study, we consider High-Level Architecture (HLA) for simulation infrastructure and fat tree topology for high-performance networking.Data Distribution Management (DDM) services are de ned under federate interface speci cations. TM service is responsible for message ordering in the time domain. DDM service is responsible for implementing effective data exchange algorithms between federates. This includes matching, message ltering, and multicast group planning. TM and DDM services are the dominating factors for network tra c and overall performance of a simulation.Initially designed for integrating different simulators together, the HLA found an alternative usage for parallelizing a single simulation. For instance, a new production line planning simulation to verify the required product quantities could be sped up by the HLA [3]. On the integration side, co-simulating analog, digital, and RF components of a System On Chip (SoC) IC is possible since the HLA framework has well de ned interfaces [4], and allows for the simple integration and testing of a variety of simulators and models. Additionally, hybrid co-simulation of Matlab Simulink continuous time domain designs and discrete event designs is also possible [5]. The simulations which are impossible to run in only one simulation environment can be easily integrated with HLA. Smart grid application for the cyber-physical energy system simulation is based on HLA to cosimulate the different simulation environments [6].Continuous time-domain application of power system and discrete event application of internet and communication technologies (ICT) co-simulation runs on a real-time environment together on HLA. An alternative would be to cosimulate the power system and ICT using the system on the loop (SITL).Although SITL provides real-time hardware-i...

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“…This approach rst calls the barrier collective communication operation to synchronize all nodes, and then the reduce-all collective communication operation to complete the GALT operation [13]. Field programmable gate arrays (FPGAs) have been employed to enhance the operation of collective communication [14], [15].…”

Section: Related Workmentioning

confidence: 99%

Network Accelerator for Parallel Discrete Event Simulations

Karaca

¹

,

İmre

²

,

Alkar

³

2022

Preprint

0

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The simulation time of parallel and distributed discrete event simulation is the heart rate for as-fast-as execution schemes. Agreeing upon a global simulation time and distributing it to the simulation processes can be improved by exploiting or redesigning the network hardware. In this paper, we present such an approach that offloads simulation time calculations to network switches in order to speed up the steps where time advance requests are made and time advance grants are waited. By reducing the waiting time for time advancement, we aim to improve the overall performance of the parallel simulations. The measurements from the FPGA-based hardware setup and the results from our network simulations show that overall performance can be improved when time management calculations are offloaded to the network switches. Additionally, the transient message problem is also solved within the network by not allowing the time control messages to bypass the time-dependent events. The network acceleration of the region-based event distribution is also studied, and offloading the region matching tasks to the network switches is found to be feasible to reduce the costs of node-based calculations, especially for fast-moving regions. In this study, we consider High-Level Architecture (HLA) for simulation infrastructure and fat tree topology for high-performance networking.

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“…Previous work has shown that significant performance speedups can be achieved by offloading collectives onto hardware. These generally enhance the NIC, [15][16][17][18] tightly connected with the processor via interconnects such as PCI, whereas the work reported here adds hardware support in the switch. For instance, Arap et al 15 offload collectives onto an FPGA cluster; however, they do not mention any communicator support, nor do they integrate into a switch.…”

Section: Related Workmentioning

confidence: 99%

“…These generally enhance the NIC, [15][16][17][18] tightly connected with the processor via interconnects such as PCI, whereas the work reported here adds hardware support in the switch. For instance, Arap et al 15 offload collectives onto an FPGA cluster; however, they do not mention any communicator support, nor do they integrate into a switch. Schmidt et al 16 implement MPI_Reduce in an FPGA cluster for the AIREN network.…”

Section: Related Workmentioning

confidence: 99%

“…First, it removes those extra layers of software (e.g., Reference 13); second, the hardware implementations can be an order-of-magnitude or more faster than the software they replace; and third, it frees up the processor for other work (e.g., Reference 14). Handling collectives in the switch, rather than in the NIC, [15][16][17][18][19] adds other advantages: it distributes the execution of collective computation throughout the network, rather than serializing it in the source (for broadcast) or the destination (for reduction); and it reduces network load as messages often only travel a single hop before being merged or duplicated.…”

mentioning

confidence: 99%

See 1 more Smart Citation

Reconfigurable switches for high performance and flexible MPI collectives

Haghi

¹

,

Guo

²

,

Xiong

³

et al. 2021

Concurrency and Computation

9

0

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There has been much effort in offloading MPI collective operations into hardware.But while NIC-based collective acceleration is well-studied, offloading their processing into the switching fabric, despite numerous advantages, has been much more limited.A major problem with fixed logic implementations is that either only a fraction of the possible collective communication is accelerated or that logic is wasted in the applications that do not need a particular capability. Using reconfigurable logic has numerous advantages: exactly the required operations can be implemented; the level of desired performance can be specified; and new, possibly complex, operations can be defined and implemented. We have designed an in-switch collective accelerator, MPI-FPGA, and demonstrated its use with seven MPI collectives and over a set of benchmarks and proxy applications (MiniApps). The accelerator uses a novel two-level switch design containing fully pipelined vectorized aggregation logic units. Essential to this work is providing support for sub-communicator collectives that enables communicators of arbitrary shape, and that is scalable to large systems. A streaming interface improves the performance for long messages. While this reconfigurable design is generally applicable, we prototype it with an FPGA-centric cluster. A sample MPI-FPGA design in a direct network achieves considerable speedups over conventional clusters in the most likely scenarios. We also present results for indirect networks with reconfigurable high-radix switches and show that this approach is competitive with SHArP technology for the subset of operations that SHArP supports. MPI-FPGA is fully integrated into MPICH and is transparent to MPI applications.

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Offloading Collective Operations to Programmable Logic on a Zynq Cluster

Cited by 8 publications

References 14 publications

Network accelerator for parallel discrete event simulations

Network accelerator for parallel discrete event simulations

Network Accelerator for Parallel Discrete Event Simulations

Reconfigurable switches for high performance and flexible MPI collectives

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