Offset Voltage Reduction Methods for a Two-Stage Folded Cascode Operational Amplifier

Stancu, Cristian; Dobrescu, D.; Dobrescu, Lidia

doi:10.1109/ecai54874.2022.9847308

Cited by 8 publications

(4 citation statements)

References 5 publications

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“…MOSFET equations for drain current and conductivity are based on the parasitic capacitance and the ratio of the width to the length of the conductor between the source and the drain, taking into account the effect of voltage as shown in the Eqs. ( 1)-(3) [28]:…”

Section: Basic Op-amps Equationsmentioning

confidence: 99%

“…These designs consist of an operational amplifier, differential amplifier, and common source amplifier with various loads, including resistive, active, and current mirror loads. Techniques for lowering the offset voltage and power consumption of a two-stage folded cascade op-amp were given by Stancu et al [28]. For low power consumption and low offset voltage, this op-amp was built with a two-stage folding cascade.…”

Section: Introductionmentioning

confidence: 99%

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Design Methodology for a Low-Power Two-Stage CMOS Operational Amplifier for Optical Receiver Applications

Hussein,

Motlak

2024

JESA

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Section: Basic Op-amps Equationsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Design Methodology for a Low-Power Two-Stage CMOS Operational Amplifier for Optical Receiver Applications

Hussein,

Motlak

2024

JESA

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“…For a given folded cascode architecture (shown in Fig. 5), the offset after fabrication can be estimated using (1) [34,35] and its variance deduced from (1) For this analysis, assume 𝐼 = 𝐼 𝐷1,2 = 𝐼 𝐷3,4 = 0.5𝐼 𝐷5,6 . It is important to remember that in MOS technology the variance of a process parameter ∆𝑝 between two identical adjacent transistors reduces inversely with the gate area and is shown in (3) [36].…”

Section: Intentional Offset Injection (Ioi)mentioning

confidence: 99%

Defect Detection and Localization in Operational Amplifiers using Digital Control and Monitor Circuits

Sekyere,

Marampally,

Chen

2023

Preprint

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Operational amplifiers (op amps) are fundamental blocks that find wide application both as stand-alone devices and as crucial building blocks embedded in various Systems on Chips (SoCs). Achieving high defect coverage as well as performing diagnosis and defect localization in these circuits has been proven to be a difficult/expensive task even with sophisticated analog and digital testing circuitry. ISO26262 Standard for functional safety (FuSa) places stringent requirement that an automotive IC must have a very high defect coverage (usually greater than 90%). This reinforce the need to improve the robustness in the design of analog and mixed signal (AMS) circuits to ensure their reliability especially if they are used in mission critical industries. This paper presents a simple defect detection, diagnosis, and localization method for op amps including Widlar current reference and biasing circuitry and can be used both for production and in-field tests for online health monitoring to ensure continued reliability during integrated circuits’ (IC) lifetime. We rigorously validate all our results using extensive transistor-level simulations of two op amps architectures (folded cascode and telescopic) designed in MUSE TSMC 180nm technology. For the folded cascode op amp, the proposed method achieves a worst-case defect coverage of 94.5% and a best-case coverage of 98%. Similarly for the telescopic op amp, the proposed method attains a worst- and best-case defect coverage of 97% and 99% respectively. Furthermore, in this work, we also propose a defect diagnosis and localization strategy using recorded bit streams from states of digital injectors and detectors.

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“…One of the op-amp's important parameters that could have an impact on the circuit behavior is the offset voltage (V OS ) [7], which is the supplementary voltage that needs to be applied at the circuit input so that the output has the desired value. In applications where the signal value at the amplifier's input is low (for example, in medical equipment) and if the V OS from the system is unfortunately high enough, the undesirable signal overlaps with the signal that needs to be processed, thus creating the premise for the wrong interpretation of the information, and a malfunction in the system could occur.…”

Section: Introductionmentioning

confidence: 99%

Offset Voltage Reduction in Two-Stage Folded-Cascode Operational Amplifier Using High-Precision Source Degeneration

Stancu,

Neacsu,

Ionescu

et al. 2023

Electronics

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The demand for CMOS precision operational amplifiers for critical applications has continuously increased over time due to higher accuracy and sensitivity requirements. Trimming or chopper architectures are advanced solutions that reduce the offset voltage and improve the circuit’s parameters, but the complexity and the increased chip die size are serious downsides. An efficient solution is a source degeneration configuration to control the transistor’s current-mirror transconductance, which impacts the offset voltage, with cost savings and a die area reduction also obtained. This paper focuses on designing and implementing such an approach in a two-stage folded-cascode operational amplifier. State-of-the-art thin-film resistors that use silicon–chromium as the metallic alloy were implemented to reduce mismatch variations between these passive components. Distinct methods that control the offset voltage parameter are also discussed and established. A comparison between the offset voltage standard deviation obtained using different types of resistors and that achieved with the innovative high-precision resistors was also carried out. The source degeneration’s impact on the common-mode rejection ratio, power supply rejection ratio, bandwidth and phase margin was also analyzed, and a comparison between the proposed design and the classical one was performed. The process variation’s influence on the circuit functionality was studied. A pre-layout ±1.273 mV maximum offset voltage at T = 27 °C was achieved using vector/array notations for the amplifier with the best overall performance. Post-layout simulations that included parasitic effects were performed, with a ±1.254 mV maximum offset voltage reached at room temperature.

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Offset Voltage Reduction Methods for a Two-Stage Folded Cascode Operational Amplifier

Cited by 8 publications

References 5 publications

Design Methodology for a Low-Power Two-Stage CMOS Operational Amplifier for Optical Receiver Applications

Design Methodology for a Low-Power Two-Stage CMOS Operational Amplifier for Optical Receiver Applications

Defect Detection and Localization in Operational Amplifiers using Digital Control and Monitor Circuits

Offset Voltage Reduction in Two-Stage Folded-Cascode Operational Amplifier Using High-Precision Source Degeneration

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