2019 IEEE 4th International Verification and Security Workshop (IVSW) 2019
DOI: 10.1109/ivsw.2019.8854391
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On a Low Cost Fault Injection Framework for Security Assessment of Cyber-Physical Systems: Clock Glitch Attacks

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Cited by 21 publications
(8 citation statements)
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“…Beside that, the physical layer security of the HC-IoT network necessitates particular deliberation, since these devices are subject to a variety of stipulations that must be overcome during the deployment phase i.e. reliable operation, quick access to the patient, low latency, and data preservation followed least implementation costs ( Dofe, Frey, Yu, 2016 , Kazemi, Papadimitriou, Souvatzoglou, Aerabi, Ahmed, Hely, Beroulle, 2019 ). As a result, high security on board is critical to meeting the above requirements during the construction process of HC-IoT devices.…”
Section: Secure Network Architecture and Authentication Approachesmentioning
confidence: 99%
“…Beside that, the physical layer security of the HC-IoT network necessitates particular deliberation, since these devices are subject to a variety of stipulations that must be overcome during the deployment phase i.e. reliable operation, quick access to the patient, low latency, and data preservation followed least implementation costs ( Dofe, Frey, Yu, 2016 , Kazemi, Papadimitriou, Souvatzoglou, Aerabi, Ahmed, Hely, Beroulle, 2019 ). As a result, high security on board is critical to meeting the above requirements during the construction process of HC-IoT devices.…”
Section: Secure Network Architecture and Authentication Approachesmentioning
confidence: 99%
“…The clock glitching attack can have a significant impact on the critical parts of a running application such as its encryption module and arithmetic or logical instructions. In several works, a specific round or operation of the AES algorithm has been targeted by a clock glitching attack to generate faulty cipher text [11,27,33]. These faulty outputs can be used to recover the encryption key.…”
Section: Clock Glitch Attack Examplesmentioning
confidence: 99%
“…Moreover, much thinner glitches can be produced by applying the CSC method due to the existing DLL constraint of generating higher frequencies for the CDCF method. As an example, [33] reported that the minimum glitch width with CSC is less than that with the CDCF method.…”
Section: Clock Glitch Generatormentioning
confidence: 99%
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“…Given a circuit, clock signal is disturbed through manipulating the clock or the voltage of the circuit. Traditionally, FIA with clock glitches is performed through the input of clock signal [4]. Recently, electromagnetic (EM) fault attack shows the capability of tampering the clock signal and inducing clock glitches [5].…”
Section: Introductionmentioning
confidence: 99%