On and Off-Chip Crosstalk Avoidance in VLSI Design

Duan, Chunjie; LaMeres, Brock J.; Khatri, Sunil P.

doi:10.1007/978-1-4419-0947-3

Cited by 31 publications

(20 citation statements)

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“…1 Another advantage of 3D ICs is that this paradigm enables the integration of CMOS circuits with disparate technologies that can be nonsilicon or even electromechanical. 2 Despite the significant advantages of 3D integration, important challenges remain such as crosstalk noise analysis and reduction, thermal mitigation, and interconnect modeling.…”

Section: Introductionmentioning

confidence: 99%

Retracted: Power macro‐modeling technique for NoC‐based homogeneous layered 3D ICs

Durrani

2017

Int J Numerical Modelling

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Section: Introductionmentioning

confidence: 99%

Retracted: Power macro‐modeling technique for NoC‐based homogeneous layered 3D ICs

Durrani

2017

Int J Numerical Modelling

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“…A number of CACs have been proposed in previous work. There are two types of CACs [31] -memory-based and memory-less. The memorybased CACs generate a codeword using not only the input data also the previous transmitted codeword.…”

Section: Crosstalk Avoidance Codes (Cacs)mentioning

confidence: 99%

Solutions to Improve the Reliability of On-Chip Interconnects

Ampadu

2011

Error Control for Network-on-Chip Links

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“…shows the basic schematic of a single-ended transmission path. Single-ended interfaces benefit from their simplicity and their low implementation cost, but have three main drawbacks [1], [4], [8], [23], [24], [25]: 1) They are highly sensitive to noise pick-up, because noise induced into the signal or ground paths adds directly to the receiver input, thus causing false receiver triggering.…”

Section: A Single-ended Signalingmentioning

confidence: 99%

“…Advantages: The usage of differential signaling has several advantages and disadvantages [1], [4], [8], [10], [26]:…”

Section: B Differential Signalingmentioning

confidence: 99%

On- and Off-chip Signaling and Synchronization Methods in Electrical Interconnects

Stojcev¹,

Dimitrijević²

2022

IJEEC

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Advances in integrated circuit (IC) fabrication technology, coupled with aggressive circuit design, have led to an exponential growth in speed and integration levels. However, to improve overall system performance, the communication speed between on-chip subsystems and between ICs in printed circuit board must increase accordingly. Currently, communication bus links in various applications approach Gbps (gigabits per second) data rates. These applications include high-speed network switching, local area network, memory buses, and multiprocessor interconnection networks. In this article, we analyze the most common (popular) CMOS implementations of high speed on- and off-chip links (electrical interconnects) and show that the links’ performance should continue to scale with technology. In addition, we point to the fact that global electrical interconnects are widely acknowledged as a limiting factor in future on-chip and off-chip designs. Novel electrical interconnect driving techniques like multi-level multi-wire signaling, and GALS synchronization method primarily intended to improve performance of on-chip electrical interconnects, has been shortly analyzed. In the future, in order to handle the electrical interconnects’ finite bandwidth (data rate higher than 100 Gbps), however, more sophisticated signaling and synchronization methods will be required.

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On and Off-Chip Crosstalk Avoidance in VLSI Design

Cited by 31 publications

References 0 publications

Retracted: Power macro‐modeling technique for NoC‐based homogeneous layered 3D ICs

Retracted: Power macro‐modeling technique for NoC‐based homogeneous layered 3D ICs

Solutions to Improve the Reliability of On-Chip Interconnects

On- and Off-chip Signaling and Synchronization Methods in Electrical Interconnects

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