Retracted: Power macro‐modeling technique for NoC‐based homogeneous layered 3D ICs

Abstract

The above article, published online on 16 November 2017 in Wiley Online Library1, has been retracted by agreement between the Editor‐in‐Chief and John Wiley & Sons. The retraction has been agreed due to major overlap with an article submitted to the Journal of Circuits, Systems, and Computers and published on 7 July 20172. The author has been informed of this action.

Power and thermal modeling approach for homogeneously stacked butterfly fat tree architecture in 3D ICs

“…The power modeling approach of BFT network is discussed in this section. The proposed model further improves these techniques, in the electrical characteristics of the network, and most of the model equations are modified as described below.…”

“…An interesting comparison of power consumption, area, throughput, and the latency among major NoC topologies is presented in Kumar et al This work is used for the trade‐off of different topologies to provide better latency and throughput at the cost of high‐power dissipation and large area. Some researchers have analyzed in Durrani and Elmiligi et al that the latency and power dissipation for fat tree, mesh, and torus network architectures may be used in digital image processing applications to generate workloads. Other researchers have compared mesh, spidergon, and ring topologies under uniform traffic patterns.…”

“…In NoC, the routers are the main bottleneck in bandwidth and power dissipation, which has been addressed in this paper. The advanced technique introduced in Durrani uses a 3D NoC analytical model on a reroute formulation for routing flows for power optimization of the network. Their results deliver the power and performance improvements over the regular 3D mesh implementations.…”